Wolfgang Wilkening

Characterization and modeling of transient device behavior under CDM ESD stress

Device physical effects that strongly influence the transient behavior during very fast, high current pulses are discussed. The effects are studied by experimental characterization and device simulation. The dependence on the technology (deep-sub-micron, smart-power/high-voltage) is considered as well. Compact models for CDM circuit simulation are developed.

Characterization and optimization of a bipolar ESD-device by measurements and simulations

Abstract The design of ESD (electro-static discharge) protection structures can be significantly shortened by using thermo-electrical device simulations. In many cases simulation results predict the performance of new designs enough accurate which makes it unnecessary to go through the whole manufacturing process of test chips. More important, however, they allow the designer to gain additional insight into a problem by examining device-internal parameters that are not obtainable through measurements, such as current densities, the electric field and the lattice temperature. In this article we investigate and optimize a p-base type npn-transistor with a vertical and a lateral operation mode. Based on the TCAD tool chain, we develop a methodology to simulate the transient switching behavior, the avalanche breakdown and the snapback holding voltages of the device. To validate our design methodology we implemented the evaluated devices on a real test chip which has also been used to gain the needed data for the calibration of the simulators. Thus we are able to compare simulation and measurements and found the simulated voltages to closely match values obtained in measurements. In addition we extracted a set of parameters for a compact circuit model describing the device under various ESD stress types.

Capacitively coupled transmission line pulsing cc-TLP: a traceable and reproducible stress method in the CDM-domain

This paper describes a new test method called Capacitively Coupled Transmission Line Pulsing cc-TLP. It is applied to different test circuits which were mounted on specially designed package emulators with a defined background capacitance. The test results are compared with the ESD thresholds obtained by CDM tests. The CC-TLP results correlate well with the CDM data.

Transient Minority Carrier Collection from the Substrate in Smart Power Design

Junction isolated logic devices in smart-power ICs collect carriers from the substrate, which may lead to malfunction and costly redesigns therefore. For the first time, minority carrier collection has been measured and simulated under transient application-near injection. Bias and measurement conditions have been varied. The largest amount of minority carriers is collected if a substrate contact close to an n-tub is grounded and/or at high temperature. 2D device simulations show reasonable agreement with measurements and reveal that an altered electric field distribution in the substrate is responsible for the drastically increased substrate current collection in case of a nearby grounded substrate contact.

ESD-level circuit simulation-impact of gate RC-delay on HBM and CDM behavior

An extraction method for the effective gate RC-delay of MOS single- and multi-finger structures is introduced by deducing a rule of thumb for the effective poly resistance. In addition to the wiring and parasitic capacitance connected to a gate, this distributed poly resistance in conjunction with the nonlinear gate capacitance can cause an appreciable gate delay (RC/spl sim/1 ns). It is demonstrated for a CMOS output driver circuit that this effect is HBM relevant. Here, circuit simulations are compared to the corresponding TLP measurements. Furthermore, a general CDM-level circuit simulation methodology is presented. To our knowledge for the first time, a CDM current source model accounts for the single pin event character of CDM. Under such stress, the simulation reveals an unexpected large impact of the gate PC-delay formed by the metal interconnects in a CMOS double input inverter. Voltage overshoots occur at internal gates and lead to oxide breakdown, which was validated by CDM stress tests and physical failure analysis.

Pulsed thermal characterization of a reverse biased pn-junction for ESD HBM simulation

Compact clectro-thermal simulation of an ESD event in a semiconductor structure requires proper definition and calibration of the equivalent thermal circuit. We demonstrate an approach to determine the device temperature during square pulse stress on the basis of the temperature dependence of the avalanche breakdown voltage. This global temperature is relevant to the transient IV-characteristic. The simulation accuracy of an HBM-stressed diode is improved significantly.

Verification of CDM circuit simulation using an ESD evaluation circuit

In this work, the capability of circuit simulation to predict CDM robustness of integrated circuits and to determine weak circuit elements is studied. The applicability is demonstrated for an ESD evaluation circuit designed to enable the analysis and optimization of ESD protection strategies in an early design phase during the introduction of a new technology. CDM circuit simulation is compared to the measurement results of variations of this circuit in two different package types. Failure locations are verified with physical failure analysis.

Test circuits for fast and reliable assessment of CDM robustness of I/O stages

CDM hardening during the development of technology, devices, libraries and finally products differs significantly from the process well-established for HBM. This paper introduces a method on the basis of specialized CDM test structures including protection elements and sensitive monitor elements. These test structures mimic typical CDM-sensitive circuits found by physical failure analysis over the years. Manufactured in five different technologies, structures were assembled in both a regular package and a new package emulator. CDM stress tests, vf-TLP tests, backside laser interferometry, device simulation, and failure analysis lead to new insights in the complex interdependencies during CDM and underline the need of CDM-specific test structures.

Modular approach of a high current MOS compact model for circuit-level ESD simulation including transient gate-coupling behaviour

Abstract A novel modular strategy for highly flexible modeling of ESD-capable MOS compact models is introduced. This high current MOS model comprises the important gate-coupling effect and an approximated formulation for the avalanche multiplication factor. This enormously enhances the computation stability and performance of the model. An easy but accurate parameter extraction procedure based upon the model equations is described. Measurement and simulation of an application example employing the new ESD-model within a CMOS output driver exhibit the relevance of dynamic gate-coupling for the ESD-reliability of the circuit.

Load Dependency Assessment of the EMC Immunity for Integrated Low Side Drivers

In automotive electronics, IC outputs are connected to a wide range of impedances generated by external circuitry or wiring harness. This load alteration, which is not fully covered by the established standard direct power injection (DPI), impacts the EMC immunity and should therefore be taken into account during susceptibility analyses. This paper introduces two S-parameter-based approaches which enable a simplified but sufficiently accurate assessment of the load dependency of the immunity. The proposed methods have been tested experimentally for a low-side driver and their validity is analyzed by comparison with measurement and large-signal simulation results.