Won D. Kim

65nm node gate pattern using attenuated phase shift mask with off-axis illumination and sub-resolution assist features

Among the valid gate pattern strategies for the 65nm technology node, att-PSM offers the advantage in cost and mask complexity over other contenders such as complimentary alt-PSM and chromeless phase lithography (CPL). A combination of Quasar illumination and sub-resolution assist features (SRAFs) provides a through pitch solution with a common depth of focus (DOF) better than 0.25um to support the aggressive scaling in both logic and high density SRAM. A global mask-source optimization scheme is adopted to explore the multi-dimensional space of process parameters and define the best overall solution that includes scanner optics such as NA and illumination, and SRAF placement rules for 1-dimensional line and space patterns through the full pitch range. Gate pattern capabilities in terms of DOF, exposure latitude, mask error enhancement factor (MEEF), optical proximity correction (OPC), CD control, and aberration sensitivity are reported in this paper. Conflict resolution and placement optimization are key to the success of implementation of SRAF to the complex 2-dimensional layouts of random logic. Reasonable CD control can be achieved based on the characterization and simulation of CD variations at different spatial and processing domains from local to across chip, across wafer, wafer-to-wafer, and lot-to-lot. Certain layout restrictions are needed for high performance devices which require a much tighter gate CD distribution. Scanner optimization and enhancement such as DoseMapper are key enablers for such aggressive CD control. The benefits, challenges, and possible extensions of this particular approach are discussed in comparison with other techniques.

Advanced reticle inspection challenges and solutions for 65nm node

Silicon Technology Development for the ITRS 65nm-node is in the final stage of an intense 2-year cycle with the full-entitlement technology qualification by the end of 2005. Accordingly, reticle technology development in support of the 65nm-node has advanced a great deal since the initial efforts began several years ago. One of the most challenging aspects of 65nm-node mask technology development is the mask inspection, which is also the main cost-driver for the 65nm-node reticle technology. As a result, controlling 65nm-node reticle cost via leveraging advanced mask inspection technologies has become a leading factor in enabling prolonged success of the 65-nm node technology for years to come. With this paper, we report our closing work on reticle inspection capability development for the 65nm-node process technology development cycle for a full-volume production ramp.

Performance of measuring contact holes using the Opti-Probe 7341 3-D RT/CD technology

Spectra of contact hole arrays with target diameters ranging from 106 to 131 nm and pattern pitch ranging from 220 to 300 nm are taken from an off-axis (65°) rotating compensator spectroscopic ellipsometry (RCSE).[1] 3-dimensional finite difference (FD3D) model developed by H. Chu,[2] is applied in the studies. To ensure accuracy of optical dispersion of each film, the simultaneous use of angle resolved beam profile reflectometry (BPR), broadband spectroscopic reflectometry (BB), and SE of an Opti-Probe 7341 are used for characterizing of the resist and BARC films. In particular, The extracted n&k dispersions are used to model the contact hole SE data using Therma-Waves proprietary 3-dimensional RT/CD technology.[3,4] The performance of stability of both static and dynamic repeatability, uniformity, and correlation to other independent technology (i.e., SEM) will be presented in this paper.

Optimization of ArF resist for 100-nm node: DOE and fine-tuning of basic platform

ArF lithography is pushing its limit to beyond the 100-nm node due to delay of NGL technologies to meet the aggressive insertion schedules. However, lithography process for 100-nm node with binary mask and ArF resist is still not easy to achieve and will be one of the big challenges for lithography community. Although there have been significant improvements over the past year, ArF resists remain as the most critical aspect in ArF lithography development. Areas of concern for ArF resist include; higher level of environmental instability compared to KrF materials, different response depending on the tone of reticles, and different performance exhibited between microsteppers used for initial development and full field scanners to be used in manufacturing. We expect that these problems will be getting worse in sub 100-nm node. To achieve the most challenging performance goals, the resist to be used in manufacturing will require optimization of the chemical formulation of commercialized resists based on specific design requirements, process and environmental conditions. This paper will describe an extensive DOE (design of experiments) that was performed in order to find better resist formulation from commercialized resists for our specific FAB environment. PAG, resin and amine were main three components for this DOE. After choosing the best resist for 100-nm node, we have will evaluated actual lithographic performance capability such as DOF, exposure latitude, etc.

193-nm thin-layer imaging performance of 140-nm contact hole patterning and DOE dry development process optimization of multilayer resist process

Thin Layer Imaging (TLI) technique offers opportunity for lithographic performance gain as well as issues relating to its complexity of the process. Of those improvement possibilities, utilizing hyper fine resolution one can gain using very thin (<250 nm) imaging layer, has been a gateway to access the otherwise unavailable sub-wavelength features using the currently available exposure tools. However, pattern transfer from the imaging layer (wet developed) to the main etch resistance layer (organic bottom layer also act as BARC, Bottom Anti Refractive Coat, during exposure) requires considerable efforts in bottom layer dry-develop etch process optimization on a plasma etch chamber. And, such an extra process requires significant amount of engineering attention to the multi layer process scheme. In this paper, we report the 140 nm (k1 equals 0.44, including true dense, 1:1 arrays) contact hole printing results (lithographic performance including resolution, focus/exposure latitudes, proximity effects) using standard binary chrome-on-quartz mask as well as the subsequent pattern transfer process optimization. The lithographic exposure was performed on a 10X ISI microstepper operating at 193 nm ArF laser source located at the RTC (Resist Test Center) of the International Sematech. The dry development DOE experiments were performed on a LAM TCP9400PTX inductively coupled plasma (ICP) etch chamber also residing at the RTC. The effect of process conditions (TCP power, bias power, O2/SO2 gas flow/ratio, and chamber pressure and chuck temperature) on the integrity of pattern transfer (etch rate, selectivity, CD bias, side wall profile) were investigated by full factor designed experiments.

Mask challenges and capability development for the 65-nm device technology node: the first status report

The slow progress of the 157nm-F2 laser exposure tool development results in broad adaptation of high numerical aperture (NA>0.8) 193nm-ArF lithography for the 65nm-node production solution. This decision, however, forces lithographers to increase dependency on very aggressive RET technologies. This in turn demands mask making capabilities the industry has never faced before such as 100nm (@4X on mask scale) size Sub Resolution Assist Features (SRAF). This report covers our early work on our mask making capability development for the 65nm-node process technology development cycle for production in 2005. Our report includes the 65nm node mask technology capability development status for mask CD and registration dimensions control, current inspection capability/issues and development efforts for critical layer masks with aggressive RET (especially of EAPSM with SRAF).

OPC rectification of random space patterns in 193-nm lithography

This paper presents a methodology for modeling the space printability at the gate level in 193nm lithography. Spaces are shown to be more susceptible to process variations and lens aberrations than lines are. Experimental Scanning Electron Microscopy (SEM) pictures show that the scum and bridging effects can occur in spaces although all the line critical dimensions (CDs) are on target. A resist imaging model is used to simulate the line CDs through defocus, pitch and size, and the prediction error is within 5nm. However, this model can not reasonably predict space CDs without using variable threshold, which is explained a proposed trajectory dissolution rate model. Based on the dissolution model, a process rule checker is proposed which inspects the peak light intensity in a space and compares it with a given threshold. This condition is verified experimentally.

Aerial image degradation effects due to imperfect sidewall profiles of EAPSM mask for 130-nm device node: 3D EMF simulations and wafer printing results

As our chip producing industry gearing up for mass production of 130nm device technology node, use of EAPSM (Embedded Attenuated Phase Shift Mask) technology in the critical pattern levels became unavoidable because of the low k1 factor lithography involved. However, this 2-layer EAPSM material (attenuator material covered with Chrome) requires two distinctively separate lithography/etch processes needed to be carried out. These added complexities of processes are prone to degradation of the absorber materials (MoSi) sidewall leading to imperfect sidewall profiles (top corner rounding, off-normal sidewall angle, etching intrusion into quartz substrate, footing, . . . etc.). These imperfections of sidewall cause aerial image degradations thus reduce effectiveness of full benefits of PSM technology. In this paper, we discuss our findings of mask level aerial image degradation dependency on EAPSM material sidewall imperfections, which result from immature mask making processes, and assessments of its effects on pattern transfer onto wafer level using 3&2D EMF and subsequent lithography simulations. The results were then, compared to actual wafer results for the wafer level printing confirmation to the simulation results. We distinguish consequence of resulting aerial image differences between EMF simulations vs. Kirchhoff approximation (treatment of absorber to be infinitely thin layer; normally used in conventional lithography simulations) in the KrF EAPSM material (MoSi). Furthermore, we have carried out look-ahead assessments for ArF (193nm) lithography using ArF EAPSM material (MoSiON) and made association between the sidewall profile variations and CD uniformity performance of EAPSM. We will make case that 3D EMF capability consideration is important in the low k1 factor lithography simulations.

CD variations from nontrivial mask-related factors

Mask critical dimension (CD) control relies on advanced write tools and resist processes. However, a specified write tool and process does not necessarily guarantee high mask quality. As the mask feature size shrinks to below 500 nm, there are other mask-related factors that can also significantly affect the mask performance. This paper discusses the impact of those non-trivial factors, such as mask writing tool and process control, calibration of mask CD metrology, blank quality of attenuated phase shift mask (ATPSM), pellicle degradation due to 193 nm laser irradiation, and profile of mask features, etc.

Mask Inspection Challenges for 90 nm and 130 nm Device Technology Nodes: Inspection Sensitivity and Printability Study using SEMI Standard Programmed Defect Masks

As our chip producing industry rapidly ramps to mass production of the 130nm device technology node and wrapping up the final stages of 90nm node process technology development, the ability to inspect all types of 130nm node masks and early identification of shortcomings in 90nm node mask inspection are extremely important. In this paper, we share our experience of mask inspection for the 90nm and 130nm nodes, using the advanced TeraStar mask inspection system (KLA-Tencor) with the SEMI programmed defect standard masks, comprising three substrate types (binary, 248nm-KrF MoSi and 193nm-ArF MoSiON). Both Die-to-Die (D2D) and Die-to-Database (DDB) inspections were carried out and the results are presented with our assessments of benefits and shortcomings of those methods. To verify the resulting defects actually impact device functionality, we also carried out systematic printability experiments with our proprietary 130nm and 90nm nodes lithography processes. The wafer results were then compared with mask inspection results and mask measurement data to draw our final conclusions. In addition, we will also present inspection performance of the TeraStar system on our 130nm production masks and very challenging 90nm node (ArF EAPSM/AAPSM) development masks.