Won-Ok Kwon

Effective digital IO pin modeling methodology based on IBIS model

IBIS (I/O buffer information specification) model is widely used in signal integrity analysis of on-board high-speed digital systems. IBIS model is converted equivalent SPICE behavioral model when used board-level simulations. It is important to represent accurately output buffers switching characteristics converting IBIS model to SPICE behavioral model. This paper proposes a new modeling algorithm to represent output buffers switching characteristics in IBIS model. The accuracy of the proposed algorithm has verified through SPICE simulation with other behavioral models.

PCI Express multi-lane de-skew logic design using embedded SERDES FPGA

Removing lane-to-lane skew is a very important function in a multi-channel receiver using high-speed serial protocols. This paper deals with implementation of data skew removing logic for the PCI Express protocol. We proposes 16 bit multi-lane de-skew logic to satisfy the PCI Express protocol specifications. This logic is optimized for general-purpose FPGA design. The proposed logic is verified by RTL simulation and implemented in an FPGA embedded programmable SERDES. The measured results agree well with the simulation results.

Efficient Server Power Supply Configuration for Cloud Computing Data Center

This paper presents a highly efficient power-redundant system for rack mount servers by changing the power backplane of the server main board. The proposed system does not need an additional redundant power supply for supporting power redundancy by sharing power at each rack mount server. In addition, the proposed power sharing architecture can provide more power efficiency than the existing rack mount server power supply.

Comparison BER with the Different Stack-up PCB of KOSMOS Micro-server System Interconnection Module Supporting 800Gbps Bandwidth

This paper is related to implementing PCB for the high-speed signal of a system interconnection module having 800Gbps bandwidth in a KOSMOS micro-server. We select the Serial RapidIO as the system interconnection network for the KOSMOS micro-server. The bandwidth of an interconnection module, which is communicating with 8 CPUs on two compute cards, is 800Gbps. The module is designed into 12 layers and 14 layers having 1.4T and 1.8T thickness with two different PCB stack-up. The implementation result shows that the high-speed signal integrity placing a signal layer between two power layers has a better quality than placing two signal layers between two power layers.

Signal integrity analysis for micorserver backplane prototype

This paper deals with high-speed serial system design methodology and measurement when designing microserver backplane system which consists many high-speed point-to-point serial protocols. A microserver is very small form factors compare with a standard rack mount server. Therefore it is required more intensive design for microserver backplane. This paper deals with signal integrity analysis about microserver backplane prototype which consists of many high-speed serial signals.

DC power shared data center configuration for cloud computing

This paper aims to improve the problems of the power of cloud computing servers used in data centers. First, we analyze the problem of power consumption of server in the cloud data center and extract the important power parameters. The second, we propose a new DC power sharing server architecture for solving the problem. Then we propose the server level DC power sharing scheme and extended to the rack and data center level DC power level shared data center architecture. The proposed DC power shared data center design is more efficient than the existing data center power architecture and can be implemented redundant power efficiently.