Woo Jin Hyun

High‐Resolution Patterning of Graphene by Screen Printing with a Silicon Stencil for Highly Flexible Printed Electronics

High-resolution screen printing of pristine graphene is introduced for the rapid fabrication of conductive lines on flexible substrates. Well-defined silicon stencils and viscosity-controlled inks facilitate the preparation of high-quality graphene patterns as narrow as 40 μm. This strategy provides an efficient method to produce highly flexible graphene electrodes for printed electronics.

All-Printed, Foldable Organic Thin-Film Transistors on Glassine Paper

All-printed, foldable organic thin-film transistors are demonstrated on glassine paper with a combination of advanced materials and processing techniques. Glassine paper provides a suitable surface for high-performance printing methods, while graphene electrodes and an ion-gel gate dielectric enable robust stability over 100 folding cycles. Altogether, this study features a practical platform for low-cost, large-area, and foldable electronics.

Screen Printing of Highly Loaded Silver Inks on Plastic Substrates Using Silicon Stencils

Screen printing is a potential technique for mass-production of printed electronics; however, improvement in printing resolution is needed for high integration and performance. In this study, screen printing of highly loaded silver ink (77 wt %) on polyimide films is studied using fine-scale silicon stencils with openings ranging from 5 to 50 μm wide. This approach enables printing of high-resolution silver lines with widths as small as 22 μm. The printed silver lines on polyimide exhibit good electrical properties with a resistivity of 5.5×10(-6) Ω cm and excellent bending tolerance for bending radii greater than 5 mm (tensile strains less than 0.75%).

High-Resolution, High-Aspect Ratio Conductive Wires Embedded in Plastic Substrates

A novel method is presented to fabricate high-resolution, high-aspect ratio metal wires embedded in a plastic substrate for flexible electronics applications. In a sequential process, high-resolution channels connected to low-resolution reservoirs are first created in a thermosetting polymer by imprint lithography. A reactive Ag ink is then inkjet-printed into the reservoirs and wicked into the channels by capillary forces. These features serve as a seed layer for copper deposition inside the channels via electroless plating. Highly conductive wires (>50% bulk metal) with minimum line width and spacing of 2 and 4 μm, respectively, and an aspect ratio of 0.6 are obtained. The embedded wires exhibit good mechanical flexibility, with minimal degradation in electrical performance after thousands of bending cycles.

Printed, 1 V electrolyte-gated transistors based on poly(3-hexylthiophene) operating at >10 kHz on plastic

Electrolyte-gated transistors (EGTs) based on poly(3-hexylthiophene) (P3HT) offer low voltage operation, high transconductance, good operational stability, and low contact resistance. These characteristics derive from the massive electrochemical or double layer capacitance (∼10–100 μF/cm2) of the electrolyte layer that serves as the gate dielectric. However, electric double layer (EDL) formation at the source/electrolyte and drain/electrolyte interfaces results in significant parasitic capacitance in EGTs which degrades dynamic switching performance. Parasitic capacitance in EGTs is reduced by covering the top surfaces of the source/drain electrodes with a low-ĸ dielectric (∼0.6 nF/cm2). The low-ĸ dielectric blocks EDL formation on the electrode surfaces that are in direct contact with the gate electrolyte, reducing the parasitic capacitance by a factor of 104 and providing a route to printed P3HT EGTs on plastic operating at switching frequencies exceeding 10u2009kHz with 1u2009V supply voltages.

All-Printed, Self-Aligned Carbon Nanotube Thin-Film Transistors on Imprinted Plastic Substrates

We present a self-aligned process for printing thin-film transistors (TFTs) on plastic with single-walled carbon nanotube (SWCNT) networks as the channel material. The SCALE (self-aligned capillarity-assisted lithography for electronics) process combines imprint lithography with inkjet printing. Specifically, inks are jetted into imprinted reservoirs, where they then flow into narrow device cavities due to capillarity. Here, we incorporate a composite high- k gate dielectric and an aligned conducting polymer gate electrode in the SCALE process to enable a smaller areal footprint than prior designs that yields low-voltage SWCNT TFTs with average p-type carrier mobilities of 4 cm2/V·s and ON/OFF current ratios of 104. Our work demonstrates the promising potential of the SCALE process to fabricate SWCNT-based TFTs with favorable I- V characteristics on plastic substrates.