Woogeun Rhee

Design of high-performance CMOS charge pumps in phase-locked loops

Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump due to the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-ended and the differential charge pumps are presented with the simulation result.

A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator

A 1.1-GHz fractional-N frequency synthesizer is implemented in 0.5-/spl mu/m CMOS employing a 3-b third-order /spl Delta//spl Sigma/ modulator. The in-band phase noise of -92 dBc/Hz at 10-kHz offset with a spur of less than -95 dBc is measured at 900.03 MHz with a phase detector frequency of 7.994 MHz and a loop bandwidth of 40 kHz. Having less than 1-Hz frequency resolution and agile switching speed, the proposed system meets the requirements of most RF applications including multislot GSM, AMPS, IS-95, and PDC.

An on-chip phase compensation technique in fractional-N frequency synthesis

Fractional-N frequency synthesis relaxes the phase-locked loop (PLL) design constraints to achieve a low noise performance while providing the same channel spacing. Inherent spurs generated by this system can be reduced with various techniques. The proposed architecture effectively compensates the periodic phase error in the time domain so that it is useful with widely used charge-pump PLLs. An on-chip tuning by a delay-locked loop (DLL) is also provided to make the system less dependent on the output frequency and process variations without using any external element. Simulation results show that the fractional spurs can be completely removed with charge-pump PLLs when ideal matching is assumed.

Design of low-jitter 1-GHz phase-locked loops for digital clock generation

A 1-GHz phase-locked loop (PLL) is implemented in 0.5-/spl mu/m CMOS to generate a 500-MHz clock with 50% duty. The voltage-controlled oscillator (VCO) combined with the differential charge pump is employed to have low clock skew and better immunity to the noises from supply, ground and substrate. The long-term peak-to-peak jitter of less than 70 psec and 165 psec are achieved for the quiet supply line and for the noisy one modulated by 400-mV/sub p-p/, 500-kHz square wave, respectively. The prototype 1-GHz PLL consumes 55 mW with 3.3-V supply. The PLL with the phase interpolation technique is also investigated and its performance is compared to the standard approach.

Integrated RF receiver front ends and frequency synthesizers for wireless

The majority of the current wireless systems operate in the 800 MHz to 2.5 GHz portion of the frequency spectrum. Typically, the handsets will employ several separate integrated circuits using a mix of technologies. With CMOS being the least expensive, the trend has been to include more functionality within the CMOS chip. However, certain portions of the transceiver have resisted the move to CMOS. In this tutorial the authors focus on two of these-the RF receiver front end with LNA and the frequency synthesizer.