Wookhyun Kwon

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

Multiple-Input Relay Design for More Compact Implementation of Digital Logic Circuits

Multiple-input relays are proposed to enable more compact implementation of digital logic circuits, and the first functional prototypes are presented. A relay with three equally sized input electrodes is demonstrated to perform various three-input logic functions, with a delay that can be well predicted by a lumped-parameter model. Relays with differently sized input electrodes can be used to perform more complex functions. A flash-type analog-to-digital converter is presented as one example.

Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells

The erase threshold-voltage (VT) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into VT transient for simulating erase VT dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller VT dispersion, compared with SA-STI. The VT dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed VT distribution, calling for examination of additional process and cell parameters

Electromechanical Diode Cell for Cross-Point Nonvolatile Memory Arrays

An electromechanical diode nonvolatile memory cell design is proposed for implementation of compact (4F2) cross-point memory arrays. The first prototype cells are demonstrated to operate with relatively low set/reset voltages and excellent retention characteristics and are multi-time programmable (with endurance exceeding 104 set/reset cycles).

Development and Optimization of Re-Oxidized Tunnel Oxide with Nitrogen Incorporation for the Flash Memory Applications

The reliability properties of NOR flash memory with 65nm node being developed in Samsung electronics are greatly improved by using the newly proposed re-oxidized tunnel oxide. Especially, by optimizing the process variables such as the re-oxidation thickness/time, the partial pressure of NO during annealing, and the kinds of re-oxidizing materials, the Vth shifts post cycling and after post-cycling bake were decreased to the level of 28% and 42% of conventional NO annealed tunnel oxide, respectively.

Variation-aware study of BJT-based capacitorless DRAM cell scaling limit

The scaling limit of the BJT-based capacitorless DRAM cell is investigated via 3-D process and device simulations, accounting for systematic and random sources of variation. The cell design and operating voltages are optimized at each gate length, following a constant electric field methodology. Retention time decreases with gate length, so that the scaling limit is expected to be 16.5 nm or 13 nm, depending on the application.

A Novel Structure for Beyond-45 nm NOR Flash Technology Featuring Short Channel Effect Immunity and Low Random Telegraph Signal Noise

We proposed a three-dimensional (3D) flash structure named recessed channel array transistor (RCAT), aiming to archive good short channel immunity and lower random telegraph signal (RTS). The results show that RCAT cell can keep a 110 nm effective gate length and consequently a punch-through voltage above 5 V even in 45 nm technology node. In RCAT cell, the RTS Vth variation was reduced from 0.5 to 0.2 V compared with planar cell due to enlarged gate length and lower channel dopant concentration. These advantages of RCAT cell make it a promising structure for the continuous scaling of the NOR flash memories to 45 nm and beyond.

The Impact of Random Telegraph Signals on the Threshold Voltage Variation of 65 nm Multilevel NOR Flash Memory

In this work, the threshold voltage (Vt) variation caused by random telegraph signals (RTS) in 65 nm multilevel (MLC) nor flash memory is discussed. The relationship of RTS amplitudes and the positions of the cells in the Vt distribution is investigated by bit mapping test method, which shows that the channel dopant fluctuation aggravates the RTS impact on the cells Vt control. Channel doping engineering is introduced to suppress RTS Vt variation in 65 nm Nor MLC flash memory. As a result, the RTS Vt variation is reduced from 0.50 to 0.26 V.

Reliable extraction of cycling induced interface states implementing realistic P/E stresses in reference cell: comparison with flash memory cell

The cycling induced interface states in floating-gate EEPROM cells are reliably extracted by implementing accurate program/erase stresses in the reference cell. The interface states measured directly from the memory cell via charge pumping are shown different from those obtained conventionally from the reference cell. The reasons for these different levels of extraction are elucidated and a new method is presented for accurate determination of interface trap density. The technique is based on introducing the equivalent gate voltage with offset voltage at the reference cell by which to simulate realistically the cycling stresses as occur in the flash memory cell itself.

Electro-Mechanical Diode Performance and Scaling for Cross-Point Non-Volatile Memory Arrays

The performance and scaling behavior of an electro- mechanical diode non-volatile memory cell design is presented. Prototype electro-mechanical diodes are demonstrated to operate with relatively low set/reset voltages and excellent retention characteristics, and are multi-time programmable. Scaling to sub-20 nm feature size is projected. Due to its simplicity, this new cell design is attractive for implementation of compact (4F2) cross-point memory arrays.