Wookyung Sun

A new bias scheme for a low power consumption ReRAM crossbar array

This paper proposes a new bias scheme for a crossbar array that can improve the power consumption and read margin. The concept of the newly proposed 5/12 bias scheme is to reduce the bias of the unselected cells for power consumption and the bias of half-selected cells for a reduced line voltage drop of the selected cell. In the 5/12 bias scheme, the unselected word line and bit line are biased to 5 × V app/12 and 7 × V app/12, respectively. The electrical characteristics of the 5/12 bias scheme are evaluated by HSPICE simulations and it is found that appropriate nonlinearity of selector can simultaneously achieve low power consumption and high read margin for 5/12 bias scheme.

Analysis of stress-induced mobility enhancement on (100)-oriented single- and double-gate n-MOSFETs using silicon-thickness-dependent deformation potential

The stress effect in uniaxially strained single- and double-gate silicon-on-insulator n-type metal oxide-semiconductor field effect transistors (MOSFETs) with a (100) wafer orientation is analyzed. A model of silicon-thickness-dependent deformation potential is introduced to accurately calculate the mobility using a Schr?dinger?Poisson solver. Simulation results using the model exhibit excellent agreement with the measured mobility for both the unstrained and strained conditions. Electron mobility enhancements with longitudinal and transverse tensile stress conditions are simulated as a function of silicon thickness. The mobility enhancement in the single-gate case has one peak point, whereas it produces two peak points in the double-gate case. An in-depth analysis reveals that this phenomenon results from the hump in the energy difference between the ?2 and ?4 valleys, which in turn results from the volume inversion in the double gate.

Investigation of power dissipation for ReRAM in crossbar array architecture

Power consumption of large-scale crossbar array architecture is investigated by the comprehensive crossbar array matrix model. The power dissipation is examined as functions of array size, leakage current of selector, and various bias schemes. The power consumption increases as the array size and the leakage current of selector increases. In addition, 1/3 bias scheme shows power consumption about 1~2 orders of magnitude larger than other bias schemes. This phenomenon is induced from the unselected cells which is delivered with voltage about Vdd/3, whereas the voltage of unselected cells are almost 0 V for 1/2 bias and floating bias schemes.

Substrate doping concentration dependence of electron mobility using the effective deformation potential in uniaxial strained nMOSFETs

The substrate doping concentration dependence of strain-enhanced electron mobility in nMOSFETs is investigated by using the effective deformation potential. The electron mobility model includes coulomb, intravalley phonon, intervalley phonon, and surface roughness scattering. The calculated results suggest that low substrate doping concentration on the (100)/<;110> nMOSFETs should be advantageous for strain-induced electron mobility enhancement at high effective electric field.

A Compact Model of Gate-Voltage-Dependent Quantum Effects in Short-Channel Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

In this paper, we present a compact model of gate-voltage-dependent quantum effects in shortchannel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson’s equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths (Lg) and radii (R). Schrodinger’s equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.

Guideline model for the bias-scheme-dependent power consumption of a resistive random access memory crossbar array

The 1/2 and 1/3 bias schemes are commonly used to select a cell in a resistive random access memory (ReRAM) crossbar array. The 1/3 bias scheme is advantageous in terms of its write margin but typically requires a higher power consumption than the 1/2 bias scheme. The power consumption of ReRAM can vary according to the nonlinearity of the selector device. In this paper, we propose a power guideline model that suggests selector nonlinearity requirements to guarantee a lower power consumption for the 1/3 bias scheme than for the 1/2 bias scheme. Therefore, the selector nonlinearity requirements for the low power consumption of the 1/3 bias scheme can be immediately obtained using this guideline model without simulation.

An analysis of the read margin and power consumption of crossbar ReRAM arrays

The read margin and power consumption for various selector characteristics and bias schemes are analyzed during read operation. The 1/2 and 1/3 bias schemes exhibit different read operation properties. There is a trade-off between the read margin and power consumption that depends on the bias scheme and characteristics of the selector. The read margin of the 1/2 bias scheme is decreased at low on/off ratios because of the output voltage drop across the LRS cell. This drop is due to a rapid increase in the leakage current when a selector with low on/off ratio is used in the 1/2 bias scheme. Therefore, the bias scheme and selector should be selected appropriately according to the purpose of the application.

A new I–V model for surrounding-gate MOSFET considering gate-voltage-dependent quantum effect

We present a new I–V model for a long-channel surrounding-gate (SG) metal–oxide–semiconductor field-effect transistor (MOSFET). SG MOSFET is a strong candidate for next generation nanoscale devices due to a high electrostatic channel control, which in turn substantially reduces the short-channel effect. The new model takes into account quantum mechanical (QM) effects in the SG MOSFET using a double triangular QM well model in the strong inversion regime. In contrast with the old model, we consider the V g dependence of the QM effect. New model yields excellent agreement with 2-D numerical simulation results for various radii and gate oxide thicknesses of the SG MOSFET.

Anomalous capacitance characteristics of TFTs with LDD structures in the saturation region

The effect of lightly doped drain (LDD) doping concentration on the capacitance of a low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is investigated. An anomalous gate-to-source capacitance phenomenon is observed: first, the capacitance decreases, and then it increases according to the gate voltage in the saturation region. This phenomenon is not affected by the subgap density-of-states and arises as the doping concentration of the LDD region is reduced. To investigate the effects of each source and the drain LDD dose on the gate-to-source capacitance, two-dimensional device simulations were conducted in which each dose of the source and drain LDD was changed individually. The reduced controllability of the source voltage to the gate charge in the saturation region due to the increased resistance of the source LDD region with low LDD dose is identified as the reason for this anomalous capacitance phenomenon.

ReRAM Crossbar Array: Reduction of Access Time by Reducing the Parasitic Capacitance of the Selector Device

The transient response of a crossbar array is investigated with HSPICE circuit simulation. A crossbar array contains many parasitic elements. This brief focuses on the parasitic capacitances of the selector devices and resistors. The read access time is determined for various array sizes and parasitic capacitances. The results show that the read access time increases with the array size and parasitic capacitance, particularly the selector capacitance. The effect of selector capacitance is analyzed with a time-dependent, unit-cell voltage model and simulation. The simulation results reveal that the selector capacitance has a greater effect than the resistor capacitance on the read access time because of the large time constant. The effect of the selector capacitance on the read access time remains significant for larger values of the other parasitic capacitances.