Wu Danyu

A 23 GHz low power VCO in SiGe BiCMOS technology

A 23 GHz voltage controlled oscillator (VCO) with very low power consumption is presented. This paper presents the design and measurement of an integrated millimeter wave VCO. This VCO employs an on-chip inductor and MOS varactor to form a high Q resonator. The VCO RFIC was implemented in a 0.18 μm 120 GHz ft SiGe hetero-junction bipolar transistor (HBT) BiCMOS technology. The VCO oscillation frequency is around 23 GHz, targeting at the ultra wideband (UWB) and short range radar applications. The core of the VCO circuit consumes 1 mA current from a 2.5 V power supply and the VCO phase noise was measured at around −94 dBc/Hz at a 1 MHz frequency offset. The FOM of the VCO is −177 dBc/Hz.

8GSps 6bit DAC in 0.18um SiGe technology

This paper describes the circuit design and measured performance of a 6-bit 8-GS/s current-steering DAC. A CML interface supporting the maximum conversion rate of 8Gbps is integrated in the chip. A PRBS-7 generator is built in the chip for synchronization as well as for data descrambling. In order to realize good linearity performance, a 2-2-2 segmental architecture is proposed for optimizing the performance. Measured DNL and INL are within +0.04/-0.12 LSB and +0.11/-0.11 LSB respectively. SFDR is above 37dBc over the Nyquist bandwidth at the sampling rate of 8 GS/s. The chip measures 1420 ×1405 um2.

A 16.9 dBm InP DHBT W-band power amplifier with more than 20 dB gain

A two-stage MMIC power amplifier has been realized by use of a 1-μm InP double heterojunction bipolar transistor (DHBT). The cascode structure, low-loss matching networks, and low-parasite cell units enhance the power gain. The optimum load impedance is determined from load-pull simulation. A coplanar waveguide transmission line is adopted for its ease of fabrication. The chip size is 1.5 × 1.7 mm2 with the emitter area of 16 × 1 μm × 15 μm in the output stage. Measurements show that small signal gain is more than 20 dB over 75.5–84.5 GHz and the saturated power is 16.9 dBm @ 79 GHz with gain of 15.2 dB. The high power gain makes it very suitable for medium power amplification.

W-band push—push monolithic frequency doubler in 1-μm InP DHBT technology

A W-band frequency doubler MMIC is designed and fabricated using 1-μm InP DHBT technology. Active balun is employed to transform the single-ended signal into differential output. Push—push configuration loaded with harmonic resonant network is utilized to acquire the second harmonic frequency. A multi-stage differential structure improves the conversion gain and suppresses the fundamental frequency. The MMIC occupies an area of 0.55 × 0.5 mm2 with 18 DHBTs integrated. Measurements show that the output power is above 5.8 dBm with the suppression of fundamental frequency below −16 dBc and the conversion gain above 4.7 dB over 75–80 GHz.

A 4 GS/s 4 bit ADC with 3.8 GHz analog bandwidth in GaAs HBT technology

An ultra-wideband 4 GS/s 4 bit analog-to-digital converter (ADC) which is fabricated in 2-level inter- connect, 1.4 m InGaP/GaAs HBT technology is presented. The ADC has a -3 dB analog bandwidth of 3.8 GHz and an effective resolution bandwidth (ERBW) of 2.6 GHz. The ADC adopts folding-interpolating architecture to minimize its size and complexity. A novel bit synchronization circuit is used in the coarse quantizer to eliminate the glitch codes of the ADC. The measurement results show that the chip achieves larger than 3.4 ENOBs with an input frequency band of DC-2.6 GHz and larger than 3.0 ENOBs within DC-4 GHz at 4 GS/s. It has 3.49 ENOBs when increasing input power by 4 dB at 6.001 GHz of input. That indicates that the ADC has the ability of sampling signals from 1st to 3rd Nyquist zones (DC-6 GHz). The measured DNL and INL are both less than 0.15 LSB. The ADC consumes power of 1.98 W and occupies a total area of 1.45 1.45 mm 2 .

A 10 Gsps 8 bit digital-to-analog converter with a built-in self-test circuit

We present a 10 Gsps 8 bit digital-to-analog converter (DAC) with a novel built-in self-test (BIST) circuit, which makes it possible to evaluate the DACs performance without a complicated test setup. Design considerations and test results are included. According to the test results, the DAC core and the BIST circuit are able to work under 10 GHz. The chip is fabricated in 0.18 μ m SiGe HBTs with f t of 100 GHz. The DAC core occupies a die size of 260×250 μ m 2 .

A 4 GHz 32 bit direct digital frequency synthesizer based on a novel architecture

This paper presents a novel direct digital frequency synthesizer (DDFS) architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collection of phase segments, the same initial value of each segment is realized by a nonlinear DAC. The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method. Then, the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment. Meanwhile, the fine ROM stores the differences between the line values and the initial value of each line. A ROM compression ratio of 32 can be achieved in the case of 11 bit phase and 9 bit amplitude. Based on the above method, a prototype chip was fabricated using 1.4 μm GaAs HBT technology. The measurement shows an average spurious-free dynamic range (SFDR) of 45 dBc, with the worst SFDR only 40.07 dBc at a 4.0 GHz clock. The chip area is 4.6 × 3.7 mm2 and it consumes 7 W from a −4.9 V power supply.

Ka-band IQ vector modulator employing GaAs HBTs

The importance of high-performance, low-cost and millimeter-wave transmitters for digital communications and radar applications is increasing. The design and performance of a Ka-band balanced in-phase and quadrature-phase (I-Q) type vector modulator, using GaAs heterojunction bipolar transistors (HBTs) as switching elements, are presented. The balanced technique is used to remove the parasitics of the HBTs to result in near perfect constellations. Measurements of the monolithic microwave integrated circuit (MMIC) chip with a size of 1.89 × 2.26 mm2 demonstrate an amplitude error below 1.5 dB and the phase error within 3° between 26 and 40 GHz except for a singular point at 35.6 GHz. The results show that the technique is suitable for millimeter-wave digital communications.

12.5 Gbps 1:16 DEMUXIC with high speed synchronizing circuits

A 12.5 Gbps 1:16 demultiplexer (DEMUX) integrated circuit is presented for multi-channel high-speed data transmission. A novel high-speed synchronizing technique is proposed and integrated in this DEMUX chip. Compared with conventional synchronizing techniques, the proposed method largely simplifies the system configuration. The experimental result demonstrates that the proposed circuit is effective in two-channel synchronization under a clock frequency of 12.5 GHz. The circuit is realized using 1 μm GaAs heterojunction bipolar transistor technology with die area of 2.3 × 2.3 mm2.

An ultra-high-speed direct digital frequency synthesizer implemented in GaAs HBT technology

This paper presents a 10-GHz 8-bit direct digital synthesizer (DDS) microwave monolithic integrated circuit implemented in 1 ?m GaAs HBT technology. The DDS takes a double-edge-trigger (DET) 8-stage pipeline accumulator with sine-weighted DAC-based ROM-less architecture, which can maximize the utilization ratio of the GaAs HBTs high-speed potential. With an output frequency up to 5 GHz, the DDS gives an average spurious free dynamic range of 23.24 dBc through the first Nyquist band, and consumes 2.4 W of DC power from a single ?4.6 V DC supply. Using 1651 GaAs HBT transistors, the total area of the DDS chip is 2.4 ? 2.0 mm2.