Xiangliang Jin

Robust dual-direction SCR with low trigger voltage, tunable holding voltage for high-voltage ESD protection

Abstract An LDNMOS-based and an LDPMOS-based dual direction silicon controlled rectifier (DDSCR) devices have been designed and fabricated in a 0.5-μm 5xa0V/18xa0V high voltage (HV) CDMOS process. These devices can be used to protect pins with a voltage range that goes above and below the ground by discharging electrostatic current in both positive and negative directions. A 2-dimension (2D) device simulation and a transmission line pulse (TLP) measurement were used to predict and characterize the ESD performance of the two DDSCR devices. Compared to LDNMOS-based DDSCR, LDPMOS-based DDSCR is excellent for its relatively low trigger voltage of 33xa0V and strong electrostatic discharge (ESD) current handling capability of 87xa0mA/μm. Furthermore, the holding voltage of LDPMOS-based DDSCR can be elevated by tuning layout parameter. Such a device has been applied to I/O bus terminals of a data interface circuit for its on-chip ESD protection.

Improvement on ESD robustness of LDMOS by bulk and source interleaved dotting

Source and bulk layout style is investigated for the purpose of improving ESD performance of multi-fingered high-voltage (HV) LDMOS. The device with bulk and source interleaved dotting (BSDOT) is fabricated in a 0.5μm 24V CDMOS process. Its ESD characteristics are studied employing transmission line pulse (TLP) measurement. Compared to traditional gate grounded nLDMOS (GG-nLDMOS) with a total length of 400μm, the proposed device can effectively increase the secondary breakdown current (It2) from 2.43A to 5.55A without any extra chip area.

Cathode Side Engineering to Raise Holding Voltage of SCR in a 0.5-㎛ 24 V CDMOS Process

A set of novel silicon controlled rectifier (SCR) devices’ characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (γ) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2- dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard 0.5-μm 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What’s more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.