Xianwei Wu

A fast fractal image encoding method based on intelligent search of standard deviation

In this paper we present a fast fractal encoding method based on an intelligent search of a Standard Deviation (STD) value between range and domain blocks. First, we describe the basic fractal image compression theory and an improved bit allocation scheme for Jacquins Iterated Function System (IFS) parameter. Experimental results show that using a Fixed Scale Parameter (FSP) can shorten encoding time without significantly affecting reconstructed image quality. Second, we present a search algorithm based on the STD introduced by Tong. We enhance Tongs STD search algorithm by introducing a domain Intelligent Classification Algorithm (ICA) based on STD-classified domain blocks. The domain block search pool is pruned by eliminating multiple domain blocks with similar STD values. We refer to this pruning as the De-Redundancy Method (DRM). The domain search process is adaptive with the range block STD value of interest controlling the size of the domain pool searched. We refer to this process as the Search Number Adaptive Control (SNAC). Finally, we present experimental results showing the efficiency of the proposed method, noting a significant improvement over Tongs original STD method without significant loss in the reconstructed image quality.

A new searchless fractal image encoding method for a real-time image compression device

In this paper, we present a new searchless iterative function system (SIFS) fractal encoding method that encodes image range blocks based on fixed location domain blocks. The advantage of this method is that the fractal code does not contain coordinates (x,y) of the domain-range matched pairs. Therefore, the size of the range block can be as small as 2/spl times/2 pixels and still maintain a good compression rate and image quality. A fractal image encoding device based on the new method is implemented and tested. Finally, the experimental results of the fractal encoding device are presented. The results show that the peak signal-to-noise ratio (PSNR) and the compression rate of the reconstructed image are as good as the traditional domain block search methods. An FPGA implementation is capable of encoding a 256/spl times/256 8-bit gray-scale image in 0.63 ms. This provides the basis for real-time fractal image compression.

Novel fractal image-encoding algorithm based on a full-binary-tree searchless iterated function system

We present a novel fractal encoding method, based on a full-binary-tree searchless iterated function system (FBSIFS), that encodes image range blocks based on a fixed-location domain block. This algorithm is capable of encoding much smaller range blocks than traditional fractal algorithms, extending to 2×2 and 2×1 range blocks or even single image pixels. The FBSIFS method employs a rectangular block decomposition, similar in nature to the more general horizontal-vertical partitioning scheme. However, the proposed method has a simpler structure, similar to quadtree partitioning. Experimental results show that this algorithm is capable of providing superior performance, in terms of encoding time, compression rate, and reconstructed image quality, to traditional search-based fractal methods. The searchless binary-tree partition method also has better performance than searchless quadtree partition methods. A comparison with existing search-based and searchless fractal algorithms is presented, including compression rate, peak SNR of the reconstructed image, and algorithm complexity. A JPEG comparison is also presented.

A multimemory access method for use in FPGA designs

In order to implement nonlinear functions including sine function and cosine functions in embedded programmable logic devices (EPLD), a memory-based lookup table is often used to obtain the correct result. However, the traditional memory-based lookup table requires a large amount of embedded array blocks (EABs). In this paper, we present an improved memory-based lookup table that reduces memory resources. This reduction allows for implementation in smaller, lower cost devices or allows for more functionality to be introduced in larger devices. We term this approach the multimemory access method (MMAM). The target device for this research is the Altera FLEX EPFI0K20RC240-4. In addition, we present an efficient VHDL-based implementation of the sine function in comparing with the MMAM algorithm to the original memory-based lookup table implementation.

Design of single stator multi-freedom piezoelectric motor device

In this paper, brings forward a new kind of piezoelectric motor device, which can perform 6 directions linear movement in a smooth plate. The motor device is driven by a single frequency electric signal, and the moving direction of the motor device can be controlled by just changing the input electrical signal. The paper first describes the principle of driving the motor. It then describes how to design the motor device that can provide the power. Finally, based on the experiments, it proves that this kind of motor device could accomplish the desired movements.