Xiao Hu Liu

A low-voltage high-speed electronic switch based on piezoelectric transduction

We propose a novel digital switch, the piezoelectronic transistor or PET. Based on properties of known materials, we predict that a nanometer-scale PET can operate at low voltages and relatively high speeds, exceeding the capabilities of any conventional field effect transistor (FET). Depending on the degree to which these attributes can be simultaneously achieved, the device has a broad array of potential applications in digital logic. The PET is a 3-terminal switch in which a gate voltage is applied to a piezoelectric (PE), resulting in expansion compressing a piezoresistive (PR) material comprising the channel, which then undergoes a continuous, reversible insulator-metal transition. The channel becomes conducting in response to the gate voltage. A high piezoelectric coefficient PE, e.g., a relaxor piezoelectric, leads to low voltage operation. Suitable channel materials manifesting a pressure-induced metal-insulator transition can be found amongst rare earth chalcogenides, transition metal oxides, and...

Chip-to-package interaction for a 90 nm Cu / PECVD low-k technology

A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBMs internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.

Evaluation of the modified edge lift-off test for adhesion characterization in microelectronic multifilm applications

The modified edge lift-off test (MELT) has gained enough acceptance in the community for evaluating interfacial adhesion that there is now commercial equipment for automating the test. However, there are several experimental and mechanics assumptions of the test that may provide unexpected outcomes. Experimental data suggested that for crack lengths greater than 5% of the film thickness the energy release rate was independent of crack length, contradicting the rule of thumb suggesting that the crack length should be greater than 10–20 times the film thickness to obtain a steady-state energy release rate in the edge crack problem. Finite element simulations not only corroborated the experimental observation but seemed to indicate that the crack length required for steady-state conditions was a function of the relative Youngs moduli for the film and substrate. It was also shown via an analytical model that plate bending (commonly neglected) can significantly affect the energy release rate in the MELT and lead to incorrect conclusions regarding the reliability of an interface.

Pathway to the piezoelectronic transduction logic device.

The piezoelectronic transistor (PET) has been proposed as a transduction device not subject to the voltage limits of field-effect transistors. The PET transduces voltage to stress, activating a facile insulator-metal transition, thereby achieving multigigahertz switching speeds, as predicted by modeling, at lower power than the comparable generation field effect transistor (FET). Here, the fabrication and measurement of the first physical PET devices are reported, showing both on/off switching and cycling. The results demonstrate the realization of a stress-based transduction principle, representing the early steps on a developmental pathway to PET technology with potential to contribute to the IT industry.

Lateral scaling of Pb(Mg1/3Nb2/3)O3-PbTiO3 thin films for piezoelectric logic applications

The dielectric and piezoelectric behavior of 70Pb(Mg1/3Nb2/3)O3-30PbTiO3 (70PMN-30PT) thin films was studied as a function of lateral scaling. Dense PMN-PT films 300–360u2009nm in thickness were prepared by chemical solution deposition using a 2-methoxyethanol solvent. These phase pure and strongly {001} oriented films exhibited dielectric constants exceeding 1400 and loss tangents of approximately 0.01. The films showed slim hysteresis loops with remanent polarizations of about 8u2009μC/cm2 and breakdown fields over 1500u2009kV/cm. Fully clamped films exhibited large signal strains of 1%, with a d33,f coefficient of 90u2009pm/V. PMN-PT films were patterned down to 200u2009nm in spatial scale with nearly vertical sidewalls via reactive ion etching. Upon lateral scaling, which produced partially declamped films, there was an increase in both small and large signal dielectric properties, including a doubling of the relative permittivity in structures with width-to-thickness aspect ratios of 0.7. In addition, declamping resulte...

Effects of failure criteria on the lifetime distribution of dual-damascene Cu line/via on W

Electromigration lifetime was studied on 0.23 μm wide Cu dual-damascene lines connected to underlying W lines with a TaN/Ta liner and SiNx/SiO2 insulator. The failure criteria used to study electromigration lifetime were based on the increase in test line resistance. Over 900 samples were tested to observe early electromigration Cu lifetime. Experimental results show that the lifetime distribution of samples tested using a failure criterion of 1% (3 Ω) resistance increase at the test temperature is best described by a trimodal function. However, the lifetime distribution of samples tested using a failure criterion of 50% is best described by a bimodal function. This difference in lifetime distribution is due to three types of observed deviant line resistance behaviors (plateau, fluctuating, and uphill) of certain samples which are caused by different types of void growth and a variation in liner stability.

Channel cracking in low-k films on patterned multi-layers

This paper considers cracking of a low-k tensile film fabricated on top of a patterned multilayer. A finite element model has been established to study all the geometry effects of the top film and underlying layers. It is found that the driving force for film cracking, as calculated from the energy release rate, is greatly enhanced by the underlying layers of copper and low-k materials. The geometry dependence has been verified by a test structure. The results indicate that a low-k film that is intact when deposited on silicon may crack when integrated in a multilayer BEOL. IBM has successfully engineered a CVD SiCOH low-k film with reduced film stress and increased modulus without degrading the cohesive strength (or the dielectric constant). Accordingly, cracking of the film has been prevented even for the worst case interconnect structures.

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.

The piezoelectronic stress transduction switch for very large-scale integration, low voltage sensor computation, and radio frequency applications

The piezoelectronic transduction switch is a device with potential as a post–CMOS transistor due to its predicted multi-GHz, low voltage performance on the VLSI-scale. However, the operating principle of the switch has wider applicability. We use theory and simulation to optimize the device across a wide range of length scales and application spaces and to understand the physics underlying its behavior. We show that the four-terminal VLSI-scale switch can operate at a line voltage of 115u2009mV while as a low voltage-large area device, ≈200u2009mV operation at clock speeds of ≈2u2009GHz can be achieved with a desirable 104 On/Off ratio—ideal for on–board computing in sensors. At yet larger scales, the device is predicted to operate as a fast (≈250 ps) radio frequency (RF) switch exhibiting high cyclability, low On resistance and low Off capacitance, resulting in a robust switch with a RF figure of merit of ≈4 fs. These performance benchmarks cannot be approached with CMOS which has reached fundamental limits. In deta...

Single Crystal Flexible Electronics Enabled by 3D Spalling

Flexible and stretchable electronics are becoming increasingly important in many emerging applications. Due to the outstanding electrical properties of single crystal semiconductors, there is great interest in releasing single crystal thin films and fabricating flexible electronics with these conventionally rigid materials. In this study the authors report a universal single crystal layer release process, called 3D spalling, extending beyond prior art. In contrast to the conventional way of removing blanket layers from their substrates, the new process reported here enables 3D control over the shape and thickness of the removed regions, allowing direct formation of arbitrarily shaped structures of released film and locally specified thickness for each region. As an exemplary demonstration, silicon flexible tactile sensors are fabricated with sensitivities comparable to those of high performance sensors on rigid substrates. Finite element modeling indicates that the size and thickness of the selectively released features can be tuned over a wide range.