Xiaojun Luo

Doherty power amplifier linearization with augmented Hammerstein model for LTE systems

In this paper, an augmented Hammerstein nonlinear model based digital pre-distortion (DPD) is utilized to linearize a Doherty power amplifier(DPA) for Long Term Evolution(LTE) system. The architecture of the augmented Hammerstein nonlinear model can be easily implement in Field Programmable Gate (FPGA). The model is composed of a look up table (LUT) and two finite impulse response (FIR) filters. Moreover, a digital predistortion platform is built to validate the effectiveness of the nonlinear model for linearizing the DPA for the LTE system. Based on the constructed platform, the accuracy of the augmented Hammerstein model is compared with those of memory polynomial (MP) model and LUT model by using a 90-W peak envelop power LDMOS field-effect-transistor Doherty power amplifier, which is driven by a LTE signal of 20MHz bandwidth and 10dB peak to average power ration (PAPR).

Memory polynomial based adaptive predistortion for Radio over Fiber systems

In this paper, a measurement apparatus based Radio-over-Fiber system prototype, including a Vector Signal Generator (VSG), a semiconductor laser, a photodetector and a spectrum analyzer, is build to study the nonlinear effects of the RoF system, which is widely regarded as a promising technique for microcell applications of the future wireless networks. The memory polynomial nonlinear model is utilized to compensate the nonlinearities in the RoF system. A three carrier Wideband Code Division Multiple Access(WCDMA) signal is applied to this test platform. The experimental results illustrate that the predistorter can improve the Adjacent Channel Power Ratio (ACPR) more than 10-dB.

A 460MHz Doherty power amplifier for IMT-Advanced systems

In this work, a Doherty power amplifier is presented for IMT-Advanced system at 450-470MHz frequency band. An imperfect Quarter-wave transmission line, which consisted of two shunt capacitors and a series microstrip line, is adopted to replace the bulky impedance inverter quarter-wave transmission line for designing the Doherty power amplifier (PA). Both the traditional and proposed structures for the Doherty power amplifiers were implemented. Comparing with the traditional Doherty amplifier, the size of the circuit and the manufacturing costs are decreased obviously. The measurement results of the proposed Doherty PA exhibit good performance as well as the traditional Doherty power amplifier. For a input signal with a 7.8dB Peak to Average Power Ratio (PAPR), the measured drain efficiency of the proposed Doherty power amplifier is 48.5% at an average output power of 43.0 dBm, which is a 7.8dB backed - off the peak output power. Moreover, in order to improve the linearity of the proposed Doherty power amplifier, the augmented Hammerstein and polynomial predistorter are used to linearize the proposed Doherty power amplifier. After digital predistortion, the adjacent channel leakage ratio (ACLR) reaches -45.5dBc at an average output power of 43.0 dBm, which can satisfy the requirements of the IMT-Advanced systems.

Asymmetrical Doherty power amplifiers for LTE-Advanced systems

In this paper, the optimization approach of a wideband and high efficiency asymmetrical Doherty power amplifier (ADPA) for LTE-Advanced systems was presented. The ADPA using the different LDMOS devices and an uneven power divider achieves constant efficiency at more than 6 dB output power back-off. The radial stubs and duplicate supply are utilized in the dc bias network to increase the bandwidth of the ADPA. The carrier amplifier (MRF8S19140) and the peaking amplifier (MRF8S19260) operate at class-AB and class-C respectively. Through ADS optimization design, the power added efficiency (PAE) is 59.064% when the maximum output power reaches 57.1 dBm at 1950MHz. At 8.5dB back-off point, the PAE is 51%. The bandwidth of the ADPA is about 145MHz ranging from 1880MHz to 2025 MHz, maintaining the gain flatness lower than ±0.5dB in small signal mode. The PAE in the whole band basically remains 45% or more for medium power level.

Optimization design of a broadband three-stage Doherty power amplifier

This paper proposes a three-stage broadband Doherty power amplifier with an extended efficiency range for TD-LTE application at 1.9–2.0GHZ. In this design, we use LDMOS devices with a power ratio of 1:1:1, The radial stubs are utilized in the dc bias network to increase the bandwidth. The power added efficiency of the proposed three-stage Doherty PA has been maintained 47% at an average output power of 46 dBm, which is 9 dB backed-off from the peak output power of 55 dBm. The simulation results clearly show that the three-stage Doherty is an efficient architecture among the various Doherty PAs, especially for a high peak to average power ratio (PAPR) signal.

A 460MHz three-stage Doherty power amplifier with uneven power driving

This paper proposes a 450–470 MHz high efficiency three-stage Doherty power amplifier for IMT-Advanced system. The input matching and output matching are achieved by utilizing microstrip line and lumped-parameter components. Two 3dB couplers are utilized to carry out uneven input power dividing so as to omit the two quarter-wave lines which are usually located before the main amplifier and the second peaking amplifier respectively. The simulation results show that the peak output power is 54.0 dBm, and the efficiency in the output power backed off 9.5dB region is effectively improved. The gain flatness can maintain ± 0.2dB in the 450–470 MHz. Moreover, another two input dividing ratio are discussed, obtaining the power additional efficiency and power gain respectively.

Optimization Design of Bias and Combiner Circuit for Asymmetrical Doherty Power Amplifiers

With the development of wireless communication systems, multi-carrier, broad band, and high transmission rate has become the development direction. To adapt to the modulation signal with high PAPR (peak to average power ratio) we propose an asymmetrical Doherty amplifier with wide bandwidth and high efficiency for LTE communication system in this paper. First, we analysis the factor of the VBW, and optimize the drain bias circuit. After optimization, the VBW is improved about 1.4 times and the amplifier will be more adaptable to the wide LTE signal. Second, we optimize the combiner structure to modulate the load impedance completely. Third, we design the asymmetrical Doherty with uneven power drive and different LDMOS devices with the optimized combiner structure. The efficiency is improved about 5% with 7 dB back-off, comparing with the traditional asymmetrical Doherty at 1.95 GHz.

Electronically Tunable Impedance-Matching Networks for Intelligent RF Power Amplifiers in Cognitive Radio Systems

This paper presents the simulation and optimization design of the electronically tunable impedance matching networks for intelligent RF power amplifiers in a cognitive radio system. Reconfigurable elements, such as varactors and RF switches are utilized to achieve the dynamic impedance matching both in the input and output matching circuit, providing coarse and fine tuning of the target impedances with low loss and excellent impedance coverage from 500MHz to 800MHz. The topology of varactor model is illustrated to ensure the precision of simulation. In addition, high-precision bias voltage controlling system is designed to improve the nonlinear problem caused by the varactor. The simulation results demonstrate the excellent performance of the tunable networks, satisfying the requirement of the cognitive radio systems.

A Dual-Band Doherty Power Amplifier for TDD Systems

This paper introduces a design of dual-band Doherty power amplifier for TDD systems. The circuit is different from single-band Doherty power amplifier. Dual characteristic impedance transformers and a novel combiner for Doherty power amplifiers are used to realize the dual-band PA in 1880-1920MHz and 2010-2025MHz. The simulation results of the PA show that the PAE achieves 52% at an average output power of 44 dBm, a 6 dB back-off output power from the peak output power of 50dBm in 1900MHz and 2017MHz simultaneously. The simulation results also clearly illustrate that this dual-band architecture is still valid for a signal with high peak to average power ratio (PAPR).

A Novel Load Network Using Imperfect Quarter-Wave Transmission Line for Three-Stage Doherty Power Amplifiers

In this work, a 460MHz three-stage Doherty power amplifier is designed for the International Mobile Telecommunications-Advanced system at 450-470MHz frequency band by using imperfect quarter-wave transmission line, which consists of two shunt capacitors and a series micro strip line to replace the bulky impedance inverter quarter-wave transmission line load network in the structure of the three-stage Doherty power amplifier. Taking 1-tone signal as input signal, the simulation results illustrate that high power added efficiency of 52% is achieved at an average output power 43.8dBm which is 9.5dB back off the peaking power. Compared with the typical three-stage Doherty power amplifier, the circuit size of the novel load network is shirked obviously. Moreover, high efficiency of the designed three stage power amplifier is also achieved at an average output power largely baked off the peaking output power by utilizing the novel load network.