Xiaoshi Jin

Modelling of the nanoscale channel length effect on the subthreshold characteristics of junctionless field-effect transistors with a symmetric double-gate structure

An analytical subthreshold current of deep nanoscale short channel junctionless field-effect transistors (JL FETs) with a symmetric double-gate (DG) structure has been proposed. It is derived from two-dimensional Poissons equation using a variable separation technique. The proposed models can exactly describe the behaviour of subthreshold I–V characteristics with nanoscale channel length without any empirical fitting parameter. The model accounts for channel length, body thickness, gate oxide thickness and body doping concentrations. The models are verified by comparison with TCAD simulations and show good agreement.

A continuous current model of fully-depleted symmetric double-gate MOSFETs considering a wide range of body doping concentrations

A continuous current model of fully-depleted symmetric double-gate (DG) MOSFETs which can reflect a wide range (from intrinsic to heavy doping) of the body doping concentrations was developed based on an approximated analytic potential solution of Poissons equation. The model was compared with the results of device simulation, and showed very good agreement in all operation regions such as subthreshold, turn-on, linear and saturation.

The Optimal Design of Junctionless Transistors with Double-Gate Structure for reducing the Effect of Band-to-Band Tunneling

The effect of band-to-band tunneling (BTBT) leads to an obvious increase of the leakage current of junctionless (JL) transistors in the OFF state. In this paper, we propose an effective method to decline the influence of BTBT with the example of ntype double gate (DG) JL metal-oxide-semiconductor field-effect transistors (MOSFETs). The leakage current is restrained by changing the geometrical shape and the physical dimension of the gate of the device. The optimal design of the JL MOSFET is indicated for reducing the effect of BTBT through simulation and analysis.

Modeling of subthreshold characteristics of short channel junctionless cylindrical surrounding-gate nanowire metal?oxide?silicon field effect transistors

A subthreshold model of short-channel junctionless field effect transistors with cylindrical surrounding-gate nanowire structure has been proposed. It was based on an approximated solution of two-dimensional Poissons equation. The derivation of this model was introduced and the accuracy of the proposed models have been verified by comparison with both previous models and the SILVACO Atlas TCAD simulation results, which show good agreement.

A continuous current model of ultra-thin cylindrical surrounding-gate inversion-mode Si nanowire nMOSFETs considering a wide range of body doping concentration

Based on the approximated solution of Poissons equation, we propose a continuous current model of ultra-thin fully depleted cylindrical surrounding-gate Si nanowire MOSFETs. It matches well with three-dimensional simulation results using SILVACO Atlas TCAD in a wide range (from intrinsic to high doping) of the body doping concentration without any empirical fitting parameters. It is valid for all the operation regions such as subthreshold, turn-on, linear and saturation.

A full analytical model of fringing-field-induced parasitic capacitance for nano-scaled MOSFETs

A full analytical model of fringing-field-induced parasitic capacitance was developed. Compared with our previous compact model, we analytically modeled the capacitance between gate electrode and source/drain including metal electrode filled in the contact holes. We used more proper conformal mapping without using approximated boundary conditions between electrode contacts. This model matches well with simulation results even when the geometrical parameters are reduced to sub-nanometers level.

Pulse Biasing Scheme for the Fast Recovery of FET-Type Gas Sensors for Reducing Gases

The promotive effect of a pre-bias condition on the recovery speed of a field-effect transistor-type gas sensor, which has a horizontal control gate (CG) and floating gate (FG), is investigated in this letter. To verify the pre-bias effect in the recovery phase after the detection of H2S gas, a type of reducing gas, a 200-nm-thick layer of SnOx is deposited on top of the interdigitated CG and FG as a sensing material. A pulse measurement method is proposed to improve the recovery speed of the sensor for H2S gas sensing by applying a negative pre-bias condition to the CG before the read operation of the sensor. This method greatly accelerates the recovery and reduces the recovery time by 74% with a pre-bias of −3 V at 180° C. The mechanism is explained in terms of energy band theory. The pre-biasing method used with our gas sensor is beneficial for the continuous monitoring and for the rapid detection of various gases.

A Gate-Induced Drain-Leakage Current Model for Fully Depleted Double-Gate MOSFETs

A gate-induced drain-leakage current model which can avoid the invalidation of 1-D models for fully depleted double-gate MOSFETs was developed based on tunneling theory and the analytical solution of a 2-D Poisson equation. For a given device geometry and a doping concentration, assuming that the drain region was fully depleted, the 2-D Poisson equation is solved using a separation-of-variable technique with appropriate boundary conditions. The results were compared with the data from a 2-D device simulation and showed good agreement.

A source drain symmetric and interchangeable bidirectional tunneling field effect transistor

A novel bidirectional tunneling field effect transistor with source drain symmetric and interchangeable functions (SDSI BT FET) is proposed in this work. Different from the conventional tunneling field effect transistors (TFET), once the absolute value of drain-to-source bias voltage is determined, no matter which of the source drain interchangeable electrode is set to be drain, the proposed SDSI BT FET brings stable and unified transfer characteristics, thereafter, shows the source drain symmetric and interchangeable functions, which makes it more compatible with CMOS circuit compared to conventional TFET. It also has inherited the advantages of conventional TFET including lower subthreshold swing, lower static power dissipation, etc. Furthermore, through design optimization, a lower reverse biased leakage current and higher Ion-Ioff ratio can be observed.A novel bidirectional tunneling field effect transistor with source drain symmetric and interchangeable functions (SDSI BT FET) is proposed in this work. Different from the conventional tunneling field effect transistors (TFET), once the absolute value of drain-to-source bias voltage is determined, no matter which of the source drain interchangeable electrode is set to be drain, the proposed SDSI BT FET brings stable and unified transfer characteristics, thereafter, shows the source drain symmetric and interchangeable functions, which makes it more compatible with CMOS circuit compared to conventional TFET. It also has inherited the advantages of conventional TFET including lower subthreshold swing, lower static power dissipation, etc. Furthermore, through design optimization, a lower reverse biased leakage current and higher Ion-Ioff ratio can be observed.