Xiaoxia Han

A low-power inverter-based ΣΔ analog-to-digital converter for audio applications

This paper presents a design for a low-power, high-resolution audio ΣΔ analog-to-digital converter (ADC) based on a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a sub-threshold amplifier, thereby minimizing power dissipation. The proposed ADC chip is fabricated in a SMIC 65-nm CMOS process with a die area of 0.63 mm2. With 1.2 V of supply voltage, the ADC chip achieves a peak signal-to-noise-plus-distortion-ratio (SNDR) of 92 dB and a dynamic range (DR) of 97 dB over the 20 kHz audio band, consuming only 1.13 mW. These results make the ADC particularly suitable for portable electronics applications.

Switched-loop filter for automatically frequency-calibrated phase-locked loops

A novel switched-loop filter, which can significantly reduce ripples on voltage controlled oscillator (VCO) control line, is proposed for phase-locked loops (PLL) with an automatic frequency calibration technique. Complementary bootstrapped transmission gates are utilized and rearranged clocks are generated to improve the performance of loop filter. Based on the SMIC 65nm RF CMOS process, the proposed switched-loop filter applicable to 0.8V to 6GHz PLL with automatic frequency calibration technique is designed. Transistor level simulation results in SPECTRE show that using the proposed switched-loop filter, ripples at VCO control line are reduced down to 2mV and the phase noise of PLL is -136.4dBc/Hz at 1MHz offset. Compared with the PLL using conventional loop filter, the control voltage ripples and the phase noise are improved by 98.8% and 29.7dB, respectively.

Unsupervised and real-time spike sorting chip for neural signal processing in hippocampal prosthesis

BACKGROUND Damage to the hippocampus will result in the loss of ability to form new long-term memories and cognitive disorders. At present, there is no effective medical treatment for this issue. Hippocampal cognitive prosthesis is proposed to replace damaged regions of the hippocampus to mimic the function of original biological tissue. This prosthesis requires a spike sorter to detect and classify spikes in the recorded neural signal. NEW METHOD A 16-channel spike sorting processor is presented in this paper, where all channels are considered as independent. An automatic threshold estimation method suitable for hardware implementation is proposed for the Osort clustering algorithm. A new distance metric is also introduced to facilitate clustering. Bayes optimal template matching classification algorithm is optimized to reduce computational complexity by introducing a preselection mechanism. RESULTS The chip was fabricated in 40-nm CMOS process with a core area of 0.0175 mm2/ch and power consumption of 19.0 μW/ch. Synthetic and realistic test data are used to evaluate the chip. The test result shows that it has high performance on both data. COMPARISON WITH EXISTING METHOD(S) Compared with the other three spike sorting processors, the proposed chip achieves the highest detection and classification accuracy. It also has the ability to deal with partially overlapping spikes, which is not reported in the other work. CONCLUSIONS We have developed a 16-channel spike sorting chip used in hippocampal prosthesis, which provides unsupervised clustering and real-time detection and classification. It also has the ability to deal with partially overlapping spikes.

ASIC Implementation of a Nonlinear Dynamical Model for Hippocampal Prosthesis

A hippocampal prosthesis is a very large scale integration (VLSI) biochip that needs to be implanted in the biological brain to solve a cognitive dysfunction. In this letter, we propose a novel low-complexity, small-area, and low-power programmable hippocampal neural network application-specific integrated circuit (ASIC) for a hippocampal prosthesis. It is based on the nonlinear dynamical model of the hippocampus: namely multi-input, multi-output (MIMO)–generalized Laguerre-Volterra model (GLVM). It can realize the real-time prediction of hippocampal neural activity. New hardware architecture, a storage space configuration scheme, low-power convolution, and gaussian random number generator modules are proposed. The ASIC is fabricated in 40 nm technology with a core area of 0.122 mm2 and test power of 84.4 μW. Compared with the design based on the traditional architecture, experimental results show that the core area of the chip is reduced by 84.94% and the core power is reduced by 24.30%.

A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process

Dear editor, Demand for higher data transmission rate, particularly in the modern communication systems, has been increasing over the years. For example, the IEEE standard 802.15.3c specifies more than 2 Gbps data transmission rate, which pushes the frequency band up to 60 GHz. In the transceiver, the working frequency of VCO is in 60 GHz, and that has attracted many people to study it [1, 2]. However, implementing high speed voltagecontrolled oscillator (VCO) through CMOS technology can be extremely challenging because of the intrinsic cut-off frequency limitation of CMOS devices. The LC-tank VCO structure can be used to address this issue [3], but its phase noise is poor and the power consumption is high [4, 5]. In the previous studies, the researchers use the intrinsictuned technique and capacitance-splitting technique to improve VCO performance, but they are complicated [6]. When the frequency increases, the power consumption of VCO will also increase significantly because the circuit nodes switch faster in different states. The Q factor of varactor will also deteriorate rapidly and cause deterioration of the VCO phase noise at a higher frequency. For example, when the working frequency changes from 2.4 GHz to 60 GHz, the Q factor of the varactor will deteriorate from 137.8 to 5.58. Therefore, determining how to improve the varactor performance is crucial for the millimeter wave VCO design. To overcome the technique difficulties, the new VCO architectures have to be explored in addition to leveraging on the traditional approaches. In this letter, we adopted the novel VCO architectures to better trade off among the performance, power and area. In order to improve the phase noise and reduce the power consumption, the low power technique is adopted in the LC tank, which can improve the Q factor of varactor. Measurement results show the novel VCO demonstrates the better figure-of-merit (FOM) compared to the traditional VCO structure. Circuit architecture. In traditional approach of VCO, two NMOS transistors constitute the negative resistance mechanism to maintain the resonator operation and two varactors are used to tune the frequency of VCO. This structure is simple but its performance and power consumption are not good enough for the high frequency applications. The main reason is the sharp deterioration of the varactor Q factor. In this let-

A V-band VCO with on-chip body bias voltage control technique using 40-nm CMOS process

Abstract This paper presents a V-band voltage-controlled oscillator (VCO) implemented in 40-nm CMOS Process. The on-chip body bias voltage control technique is adopted to improve phase noise and stability of the output signal and to design an LC tank and output buffer circuitry that compensates for the process, voltage, and temperature variations. The design was fabricated in RF Mixed-signal CMOS process with die size 0.078 mm2. Based on the silicon results, the proposed VCO achieve a phase noise of −86 dBc/Hz at 1 MHz offset. The VCO draws 17.8 mA current from a 1.2 V supply. Compared with the traditional structure VCO of the same batch, the measured figure of merit (FOM) is optimized from −165.4 to −169 dB. The novel VCO demonstrates better FOM performance compared to the traditional VCO structure. Moreover, the measured output signal power offset of novel VCO is reduced by 1.8 dBm, which will contribute to the improvement in the yield of chip manufacturing.

A V-band 40 nm CMOS phase locked loop with mutual injection locking technique

This paper presents a V-band phase-locked loop (PLL) that employs zero blind zone phase frequency detector (PFD) and mutual injection-locking voltage controlled oscillator (VCO) to improve signal quality performance. This architecture is fabricated in 40-nm CMOS process with a die area of 0.7 mm2. The silicon results demonstrate an excellent in-band phase noise of −90 dBc/Hz at 500 kHz offset with 2.5 MHz bandwidth. The PLL draws 40.8 mA current (including output buffer) from a 1.2 V power supply while operating at 60.8 GHz.