Xiaoxin Xu

Evolution of conductive filament and its impact on reliability issues in oxide-electrolyte based resistive random access memory

The electrochemical metallization cell, also referred to as conductive bridge random access memory, is considered to be a promising candidate or complementary component to the traditional charge based memory. As such, it is receiving additional focus to accelerate the commercialization process. To create a successful mass product, reliability issues must first be rigorously solved. In-depth understanding of the failure behavior of the ECM is essential for performance optimization. Here, we reveal the degradation of high resistance state behaves as the majority cases of the endurance failure of the HfO2 electrolyte based ECM cell. High resolution transmission electron microscopy was used to characterize the change in filament nature after repetitive switching cycles. The result showed that Cu accumulation inside the filament played a dominant role in switching failure, which was further supported by measuring the retention of cycle dependent high resistance state and low resistance state. The clarified physical picture of filament evolution provides a basic understanding of the mechanisms of endurance and retention failure, and the relationship between them. Based on these results, applicable approaches for performance optimization can be implicatively developed, ranging from material tailoring to structure engineering and algorithm design.

Uniformity Improvement in 1T1R RRAM With Gate Voltage Ramp Programming

Uniformity is one of the most severe challenges for resistive random access memory (RRAM). In this letter, a novel programming scheme with gate voltage ramping (GVR) is proposed to improve the uniformity of RRAM in a one transistor and one resistor structure. In traditional operation, the gate of the access transistor is biased with a constant voltage and a sweeping voltage is applied to the source or drain during the SET (from HRS to LRS) and RESET (from LRS to HRS) processes. With the GVR scheme, the gate voltage VG is ramped and the source/drain are kept constant. A tight distribution of HRS can be achieved using GVR. Analysis of power generation in the RESET process of the GVR scheme reveals positive feedback from joule heating, which helps to accelerate filament rupture and results in a tendency to achieve full RESET. The intermediate resistance states commonly observed are effectively eliminated.

Atomic View of Filament Growth in Electrochemical Memristive Elements

Memristive devices, with a fusion of memory and logic functions, provide good opportunities for configuring new concepts computing. However, progress towards paradigm evolution has been delayed due to the limited understanding of the underlying operating mechanism. The stochastic nature and fast growth of localized conductive filament bring difficulties to capture the detailed information on its growth kinetics. In this work, refined programming scheme with real-time current regulation was proposed to study the detailed information on the filament growth. By such, discrete tunneling and quantized conduction were observed. The filament was found to grow with a unit length, matching with the hopping conduction of Cu ions between interstitial sites of HfO2 lattice. The physical nature of the formed filament was characterized by high resolution transmission electron microscopy. Copper rich conical filament with decreasing concentration from center to edge was identified. Based on these results, a clear picture of filament growth from atomic view could be drawn to account for the resistance modulation of oxide electrolyte based electrochemical memristive elements.

Set statistics in conductive bridge random access memory device with Cu/HfO2/Pt structure

The switching parameter variation of resistive switching memory is one of the most important challenges in its application. In this letter, we have studied the set statistics of conductive bridge random access memory with a Cu/HfO2/Pt structure. The experimental distributions of the set parameters in several off resistance ranges are shown to nicely fit a Weibull model. The Weibull slopes of the set voltage and current increase and decrease logarithmically with off resistance, respectively. This experimental behavior is perfectly captured by a Monte Carlo simulator based on the cell-based set voltage statistics model and the Quantum Point Contact electron transport model. Our work provides indications for the improvement of the switching uniformity.

Superior Retention of Low-Resistance State in Conductive Bridge Random Access Memory With Single Filament Formation

Data retention is one crucial reliability aspect of resistive random access memory (RRAM). The retention failure mechanism of the low-resistance state (LRS) for conductive bridge RAM is generally originated from the lateral diffusion of metal ions/atoms from the filament to its surrounding medium. In this letter, we proposed an effective method to improve the LRS retention by controlling the formation of the single filament. For a certain LRS, the effective surface area for metal ions/atoms diffusion in single filament is less than that of multi-filament. Thus, better LRS retention characteristics can be achieved by reducing the metal species diffusion. The validity of this method is verified by the superior retention characteristics of the LRS programmed by current mode, in comparison with voltage programming mode. The former tends to generate a single filament, while the later grows multi-filament. This letter provides a possible way to enhance the retention characteristics of RRAM.

Improving resistance uniformity and endurance of resistive switching memory by accurately controlling the stress time of pulse program operation

In this letter, the impact of stress time of pulse program operation on the resistance uniformity and endurance of resistive random access memory (RRAM) is investigated. A width-adjusting pulse operation (WAPO) method which can accurately setup and measure switching time is proposed for improving the uniformity and endurance of RRAM. Different from the traditional single pulse operation (TSPO) method in which only one wide pulse is applied in each switching cycle, WAPO method utilizes a series of pulses with the width increased gradually until a set or reset switching process is completely finished and no excessive stress is produced. Our program/erase (P/E) method can exactly control the switching time and the final resistance and can significantly improve the uniformity, stability, and endurance of RRAM device. Improving resistance uniformity by WAPO compared with TSPO method is explained through the interdependence between resistance state and switching time. The endurance improvement by WAPO operation stems from the effective avoidance of the overstress-induced progressive-breakdown and even hard-breakdown to the conductive soft-breakdown path.

Occurrence of Resistive Switching and Threshold Switching in Atomic Layer Deposited Ultrathin (2 nm) Aluminium Oxide Crossbar Resistive Random Access Memory

Resistive random access memory (RRAM) is a promising emerging nonvolatile memory which offer high density integration in the form of cross-bar array design. Selector devices are a vital requirement to suppress the cross-talk issue. In this letter, we are going to demonstrate the coexistence of resistive switching (RS) and threshold switching (TS) in an ultrathin 2-nm Aluminium oxide (AlOx)-based crossbar RRAM devices. Depending on current level the device itself can switch from TS to RS mode with a nonlinearity of > 102. Stable TS of > 103 cycles has been achieved at 10 nA. Achievements of this letter offers the usability of 2-nm AlOx RRAM devices as a selector and as a memory device for high density crossbar array integration.

Cu BEOL compatible selector with high selectivity (>107), extremely low off-current (∼pA) and high endurance (>1010)

Selector with high nonlinearity and low leakage current is critical to solve the sneaking current issue in crossbar memory array. In this work, we present a high performance Cu BEOL compatible threshold switching (TS) selector with several outstanding features, such as high nonlinearity (~107), ultra-low off-state leakage current (~pA), robust endurance (> 1010), and sufficient on-state current density (~1 MA/cm2). The observed threshold switching is resulted from the spontaneously rupture of conductive filament in doped HfO2 material. By introducing a tunneling layer in series with the TS layer, the leakage current of the selector is dramatically reduced by more than 5 orders of magnitude. The array level benchmark of this TS selector qualifies its promising potential for 3D storage application.

Impact of program/erase operation on the performances of oxide-based resistive switching memory

Further performance improvement is necessary for resistive random access memory (RRAM) to realize its commercialization. In this work, a novel pulse operation method is proposed to improve the performance of RRAM based on Ti/HfO2/Pt structure. In the DC voltage sweep of the RRAM device, the SET transition is abrupt under positive bias. If current sweep with positive bias is utilized in SET process, the SET switching will become gradual, so SET is current controlled. In the negative voltage sweep for RESET process, the change of current with applied voltage is gradual, so RESET is voltage controlled. Current sweep SET and voltage sweep RESET shows better controllability on the parameter variation. Considering the SET/RESET characteristics in DC sweep, in the corresponding pulse operation, the width and height of the pulse series can be adjusted to control the SET and RESET process, respectively. Our new method is different from the traditional pulse operation in which both the width and height of program/erase pulse are simply kept constant which would lead to unnecessary damage to the device. In our new method, in each program or erase operation, a series of pulses with the width/height gradually increased are made use of to fully finish the SET/RESET switching but no excessive stress is generated at the same time, so width/height-controlled accurate SET/RESET can be achieved. Through the operation, the uniformity and endurance of the RRAM device has been significantly improved.

Demonstration of 3D vertical RRAM with ultra low-leakage, high-selectivity and self-compliance memory cells

Developing high performance self-selective cell (SSC) is one of the most critical issues of the integration of 3D vertical RRAM (V-RRAM). In this work, a four-layer V-RRAM array, with high performance HfO2/mixed ionic and electronic conductor (MIEC) bilayer SSC, was demonstrated for the first time. Several salient features were achieved, including ultra-low half-select leakage (<;0.1 pA), very high nonlinearity (>103), low operation current (nA level), self-compliance, high endurance (>107), and robust read/write disturbance immunity.