Xilin Liu

A Fully Integrated Wireless Compressed Sensing Neural Signal Acquisition System for Chronic Recording and Brain Machine Interface

Reliable, multi-channel neural recording is critical to the neuroscience research and clinical treatment. However, most hardware development of fully integrated, multi-channel wireless neural recorders to-date, is still in the proof-of-concept stage. To be ready for practical use, the trade-offs between performance, power consumption, device size, robustness, and compatibility need to be carefully taken into account. This paper presents an optimized wireless compressed sensing neural signal recording system. The system takes advantages of both custom integrated circuits and universal compatible wireless solutions. The proposed system includes an implantable wireless system-on-chip (SoC) and an external wireless relay. The SoC integrates 16-channel low-noise neural amplifiers, programmable filters and gain stages, a SAR ADC, a real-time compressed sensing module, and a near field wireless power and data transmission link. The external relay integrates a 32 bit low-power microcontroller with Bluetooth 4.0 wireless module, a programming interface, and an inductive charging unit. The SoC achieves high signal recording quality with minimized power consumption, while reducing the risk of infection from through-skin connectors. The external relay maximizes the compatibility and programmability. The proposed compressed sensing module is highly configurable, featuring a SNDR of 9.78 dB with a compression ratio of 8×. The SoC has been fabricated in a 180 nm standard CMOS technology, occupying 2.1 mm × 0.6 mm silicon area. A pre-implantable system has been assembled to demonstrate the proposed paradigm. The developed system has been successfully used for long-term wireless neural recording in freely behaving rhesus monkey.

The PennBMBI: Design of a General Purpose Wireless Brain-Machine-Brain Interface System

In this paper, a general purpose wireless Brain- Machine -Brain Interface (BMBI) system is presented. The system integrates four battery-powered wireless devices for the implementation of a closed-loop sensorimotor neural interface, including a neural signal analyzer, a neural stimulator, a body-area sensor node and a graphic user interface implemented on the PC end. The neural signal analyzer features a four channel analog front-end with configurable bandpass filter, gain stage, digitization resolution, and sampling rate. The target frequency band is configurable from EEG to single unit activity. A noise floor of 4.69 μVrms is achieved over a bandwidth from 0.05 Hz to 6 kHz . Digital filtering, neural feature extraction, spike detection, sensing-stimulating modulation, and compressed sensing measurement are realized in a central processing unit integrated in the analyzer. A flash memory card is also integrated in the analyzer. A 2-channel neural stimulator with a compliance voltage up to ±12 V is included. The stimulator is capable of delivering unipolar or bipolar, charge-balanced current pulses with programmable pulse shape, amplitude, width, pulse train frequency and latency. A multi-functional sensor node, including an accelerometer, a temperature sensor, a flexiforce sensor and a general sensor extension port has been designed. A computer interface is designed to monitor, control and configure all aforementioned devices via a wireless link, according to a custom designed communication protocol. Wireless closed-loop operation between the sensory devices, neural stimulator, and neural signal analyzer can be configured. The proposed system was designed to link two sites in the brain, bridging the brain and external hardware, as well as creating new sensory and motor pathways for clinical practice. Bench test and in vivo experiments are performed to verify the functions and performances of the system.

Design of a low-noise, high power efficiency neural recording front-end with an integrated real-time compressed sensing unit

This paper presents a 12-channel, low-power, high efficiency neural signal acquisition front-end for local field potential and action potential signals recording. The proposed neural front-end integrates low noise instrumentation amplifiers, low-power filter stages with configurable gain and cut-off frequencies, a successive approximation register (SAR) ADC, and a realtime compressed sensing processing unit. A capacitor coupled instrumentation amplifier integrated input impedance boosting has been designed, dissipating 1μA quiescent current. An input referred noise of 1.63μV was measured in the frequency band of 1Hz to 7kHz. The noise efficiency factor (NEF) of the amplifier is 0.76. The SAR ADC achieves an ENOB of 10.6-bit at a sampling rate of 1MS/s. A compressed sensing processing unit with configurable compression ratio, up to 8x, was integrated in the design. The design has been fabricated in 180nm CMOS, occupying 4.5mm×1.5mm silicon area. A portable neural recorder has been built with the custom IC and a commercial low-power wireless module. A 4.6g lithium battery supports the device for a continuous compressed sensing recording up to 70 hours.

The PennBMBI: A general purpose wireless Brain-Machine-Brain Interface system for unrestrained animals

In this paper, a general purpose wireless Brain-Machine-Brain Interface (BMBI) system is proposed. The system provides all the necessary hardware for a closed-loop sensorimotor neural interface. The system integrates a neural signal analyzer, two neural stimulators with different specifications, multiple body area sensory devices and a user-friendly computer interface. The neural signal analyzer features four channel analog frontend with configurable bandpass filter, gain stage, digitization resolution, and sampling rate. Digital filtering, neural feature extraction, spike detection, sensing-stimulating modulation, and compressed sensing measurement are realized in a central processing unit integrated in the analyzer. Flash memory card is activated for low power operation, compressed sensing recovery verification and/or data backup. An 8-channel stimulator with high driving capability (±10 mA with compliance voltage ±22V), and a 2-channel stimulator for deep brain stimulation are included in the proposed system. Both stimulators are capable of delivering bipolar, biphasic capacitive coupled current pulses in programmable pulse shape, amplitude, width, pulse train frequency and latency. Multi-functional wireless sensor node, including an accelerometer, a temperature sensor, and a general sensor extension port has been designed. Surveillance camera is implemented for the monitoring of the animals behavior. A userfriendly computer interface is designed to monitor, control and configure all aforementioned devices via wireless link. Wireless closed-loop operation between the sensory devices, neural stimulators, and neural signal analyzer can be configured. Bench test and in vivo experiments are performed to verify the functions and performance of the system.

The effects of acute cortical somatosensory deafferentation on grip force control.

Grip force control involves mechanisms to adjust to unpredictable and predictable changes in loads during manual manipulation. Somatosensory feedback is critical not just to reactive, feedback control but also to updating the internal representations needed for proactive, feedforward control. The role of primary somatosensory cortex (S1) in these control strategies is not well established. Here we investigated grip force control in a rare case of acute central deafferentation following resection of S1. The subject had complete loss of somatosensation in the right arm without any deficit in muscle strength or reflexes. In the first task, the subject was asked to maintain a constant grip force with and without visual feedback. The subject was able to attain the target force with visual feedback but not maintain that force for more than a few seconds after visual feedback was removed. In the second task, the subject was asked to grip and move an instrumented object. The induced acceleration-dependent loads were countered by adjustments in grip force. Both amplitude and timing of the grip force modulation were not affected by deafferentation. The dissociation of these effects demonstrates the differential contribution of S1 to the mechanisms of grip force control.

A Low-Power Multifunctional CMOS Sensor Node for an Electronic Facade

In this paper, a low-power, multifunctional CMOS smart sensor node is designed for an electronic facade, which provides an alternative solution to the concept of energy-efficient responsive buildings. Various sensing capabilities, including light intensity sensing, temperature sensing, motion tracking, and compressive image acquisition, are implemented on the sensor node. An 80 × 80 image pixel array is employed for motion tracking and compressive image acquisition. Various operational modes are realized, including: 1) event generation mode; 2) motion tracking mode; and 3) video output mode in full-resolution or compressed by the region of interest (ROI). A low-power, high-throughput motion detection algorithm is proposed in this paper. The power consumption of the proposed work is modeled, analyzed, and compared with traditional motion detection methods. According to numerical analysis, the throughput can be increased by 45% while using the proposed design instead of traditional temporal differential motion tracking methods with simislar power consumption. The proposed algorithm is realized by a pixel-level focal-plane motion detection unit, consisting of switched-capacitor circuit, analog memory, and dual-threshold comparator. The proposed design was fabricated in 0.5 μm 3M2P standard CMOS technology, occupying 3×3 mm2 silicon area. The total power consumption is 17 μW, while the pixel array is performing motion tracking with a frame rate of 30 fps and a supply voltage of 3.3 V.

The Virtual Trackpad: An Electromyography-Based, Wireless, Real-Time, Low-Power, Embedded Hand-Gesture-Recognition System Using an Event-Driven Artificial Neural Network

This brief presents a wireless, low-power embedded system that recognizes hand gestures by decoding surface electromyography (EMG) signals. Ten hand gestures used on commercial trackpads, including pinch, stretch, swipe left, swipe right, scroll up, scroll down, single click, double click, pat, and ok, can be recognized in real time. Features from four differential EMG channels are extracted in multiple time windows. Unlike traditional data segmentation methods, an event-driven method is proposed, with the gesture event detected in the hardware. Feature extraction is triggered only when an event is detected, minimizing computation, memory, and system power. A time-delayed artificial neural network (ANN) is used to predict the gesture from the transient EMG features instead of traditional steady-state features. The ANN is implemented in the microcontroller with a processing time less than 0.2 ms. The detection results are sent wirelessly to a computer. The device weights 15.2 g. A 4.6 g battery supports up to 40 h continuous operation. To our knowledge, this brief shows the first real-time, embedded hand-gesture-recognition system using only transient EMG signals. Experiments with four subjects show that the device can achieve a recognition of ten gestures with an average accuracy of 94%.

Design of a net-zero charge neural stimulator with feedback control

This paper presents a high efficiency, net-zero charge neural stimulator. A new stimulation strategy is proposed to reduce the charge error that originates from the irreversible charge diffusion, which is a common issue in traditional current matching stimulator designs. In addition, an arbitrary channel configuration of the working and counter electrodes is achieved. Two methodologies are applied to the proposed design to increase the stimulation efficiency: i) feedback control of an adaptive driving voltage, which enables a constant low operating voltage for the entire active circuits; ii) charge recycling, which “recycles” the accumulated charges on the blocking capacitor. An improved current mode DAC and a digital feed-forward error compensation comparator are integrated in the output stage to suppress the process variation, and minimize the charge error in continuous stimulation pulse trains. Performance characterization and invivo experimental result of a prototype chip fabricated in standard 180nm CMOS technology are presented. An efficiency improvement of 51% is measured in the experiment.

A low power multi-mode CMOS image sensor with integrated on-chip motion detection

In this paper, we propose a novel low power multimode CMOS smart image sensor node with integrated focal-plane motion detection and video compression. An 80×80 image pixel array is fabricated in 0.5 μm 3M2P standard CMOS technology, occupying 3×3 mm2 silicon area. The proposed imager enables various operational modes, including 1) event generator mode, 2) motion tracking mode and 3) video output mode in full-resolution or compression by region of interest (ROI). An ultra low power focal-plane motion detection block, consisting of analog memory and dual-threshold comparator, is integrated in the pixel-level circuit for on-chip motion detection. A hardware-friendly motion tracking algorithm is developed that indicates ROIs according to a strategy based on the detection results. A 12-bit on-chip, off-array ADC is employed to convert the captured light intensity into digital readouts. In order to further reduce the power consumption, lower image resolution is used under the first two modes. A trade-off analysis between the image resolution and detection accuracy is proposed in this paper. In simulation, the total power consumption is 10μW at a frame rate of 30fps and a supply voltage of 3.3V in motion tracking mode. A compression ratio of 14% and an average PSNR of 42dB is achieved in compressive video output mode.

A 12-channel bidirectional neural interface chip with integrated channel-level feature extraction and PID controller for closed-loop operation

This paper presents a bidirectional neural interface, consisting of 12-channel low-noise amplifiers, channel-level neural feature extraction and proportional-integral-derivative (PID) controller, voltage and current mode analog-to-digital converters (ADC), and 12-channel multi-mode stimulators. The neural amplifier features a wide-band from 0.5Hz to 10kHz with a noise floor of 3.02μVrms. The input stage has been designed for high stimulation voltage tolerance, and fast stimulation artifact recovery. The digitally assisted, analog parallel feature extraction processor features an ultra low power consumption while performing 1) neural signal energy extraction in programmable frequency band and time window, or 2) action potential detection using a current-mode time-amplitude window discriminator. A programmable PID controller has been implemented at the channel-level for closed-loop operation. A 640nW 8-bit current-mode ADC featuring a FoM of 10.7fJ/conv-step at a sampling rate of 250kSps has been designed for action potential digitization, and a voltage-mode SAR ADC with a ENOB of 9.1 and FoM of 34.2fJ/conv-step has been implemented for neural features and local field potential digitizations. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4mA and a compliance voltage up to +/-5V in arbitrary channel configuration. The chip has been fabricated in 0.18μm HV-CMOS technology, occupying a silicon area of 2.2 mm2. The whole chip dissipates 276μW on average. Bench testing, in-vitro and in-vivo experimental results are presented in this paper.