Xinchun Liu

A Reconfigurable Accelerator for Smith–Waterman Algorithm

Scanning bio-sequence database and finding similarities among DNA and protein sequences is basic and important work in bioinformatics field. To solve this problem, Needleman-Wunschh (NW) algorithm is a classical and precise tool, and Smith-Waterman (SW) algorithm is more practical for its capability to find similarities between subsequences. Such algorithms have computational complexity proportional to the length product of both involved sequences, hence processing time becomes insufferable due to exponential growth speed and great amount of bio-sequence database. To alleviate this serious problem, a reconfigurable accelerator for SW algorithm is presented. In the accelerator, a modified equation is proposed to improve mapping efficiency of a processing element (PE), and a special floor plan is applied to a fine-grain parallel PE array and interface components to cut down their routing delay. Basing on the two techniques, the proposed accelerator can reach at 82-MHz frequency in an Altera EP1S30 device. Experiments demonstrate the accelerator provides more than 330 speedup as compared to a standard desktop platform with a 2.8-GHz Xeon processor and 4-GB memory and has 50% improvement on the peak performance of a transferred traditional implementation without using the two special techniques. Our implementation is also about 9% faster than the fastest implementation in a most recent family of SW algorithm accelerators.

A Reconfigurable Index FLASH Memory tailored to Seed-Based Genomic Sequence Comparison Algorithms

Genomic sequence comparison algorithms represent the basic toolbox for processing large volume of DNA or protein sequences. They are involved both in the systematic scan of databases, mostly for detecting similarities with an unknown sequence, and in preliminary processing before advanced bioinformatics analysis. Due to the exponential growth of genomic data, new solutions are required to keep the computation time reasonable. This paper presents a specific hardware architecture to speed-up seed-based algorithms which are currently the most popular heuristics for detecting alignments. The architecture regroups FLASH and FPGA technologies on a common support, allowing a large amount of data to be rapidly accessed and quickly processed. Experiments on database search and intensive sequence comparison demonstrate a good cost/performance ratio compared to standard approaches.

Survey on index based homology search algorithms

Abstract Up to now, there are many homology search algorithms that have been investigated and studied. However, a good classification method and a comprehensive comparison for these algorithms are absent. This is especially true for index based homology search algorithms. The paper briefly introduces main index construction methods. According to index construction methods, index based homology search algorithms are classified into three categories, i.e., length based index ones, transformation based index ones, and their combination. Based on the classification, the characteristics of the currently popular index based homology search algorithms are compared and analyzed. At the same time, several promising and new index techniques are also discussed. As a whole, the paper provides a survey on index based homology search algorithms.

Short read DNA fragment anchoring algorithm

BackgroundThe emerging next-generation sequencing method based on PCR technology boosts genome sequencing speed considerably, the expense is also get decreased. It has been utilized to address a broad range of bioinformatics problems. Limited by reliable output sequence length of next-generation sequencing technologies, we are confined to study gene fragments with 30~50 bps in general and it is relatively shorter than traditional gene fragment length. Anchoring gene fragments in long reference sequence is an essential and prerequisite step for further assembly and analysis works. Due to the sheer number of fragments produced by next-generation sequencing technologies and the huge size of reference sequences, anchoring would rapidly becoming a computational bottleneck.Results and discussionWe compared algorithm efficiency on BLAT, SOAP and EMBF. The efficiency is defined as the count of total output results divided by time consumed to retrieve them. The data show that our algorithm EMBF have 3~4 times efficiency advantage over SOAP, and at least 150 times over BLAT. Moreover, when the reference sequence size is increased, the efficiency of SOAP will get degraded as far as 30%, while EMBF have preferable increasing tendency.ConclusionIn conclusion, we deem that EMBF is more suitable for short fragment anchoring problem where result completeness and accuracy is predominant and the reference sequences are relatively large.

Fast and Compact Regular Expression Matching Using Character Substitution

Regular expression (Reg Ex) matching plays an important role in many modern intrusion detection systems (IDS). DFA is an effective way to perform regular expression matching. However, the prohibitive memory requirement makes DFAs impractical for many real world rule sets. In this paper we propose a method to dramatically reduce the DFA memory usage and still provide guaranteed matching speed. A small table for each state is employed to help translate the input character into the offset of the modified transition table for the same state. The proposed representation for DFAs is called character substitution DFA (CSDFA). We present experimental results using rule sets from both L7-filter and Snort.

HPP Switch: A Novel High Performance Switch for HPC

The high performance switch plays a critical role in the high performance computer (HPC) system. The applications of HPC not only demand on the low latency and high bandwidth of the switch, but also need the effective support of collective communication, such as broadcast, multicast, and barrier etc. In this paper, HPP switch, as the core component of interconnection network of a HPC prototype, is introduced to meet these requirements. It is with 38.4 ns zero-load latency, 160 Gbps aggregated bandwidth, 16 multicast groups and 16 barrier groups. HPP switch is implemented in a 0.13 mum CMOS standard cell ASIC technology. The simulation results show that the multicast and barrier operations for 1024 nodes are finished within 2 mus, and the single stage of barrier operation only needs 128 ns.

The architecture of a specific chip for RNA secondary structure prediction

The architecture of a BioAccel (internal code) chip for RNA secondary structure prediction is described in the letter. The system is based on a BioBus (internal code), whose distinguishing features are: Two separated control and data channels, and a slave-associated arbitration scheme. Two reference systems based on the AMBA AHB bus and Coreconnect bus are introduced to evaluate the performance of the system. The simulation results are attractive. The average communication bandwidth of the chip is increased at severalfold, and the read and write latencies are reduced about 40 percent.

An efficient dynamic programming algorithm and implementation for RNA secondary structure prediction

RNA secondary structure prediction based on free energy rules for stacking and loop conformation remains a major computational method. The basic dynamic programming algorithm needs O(n4) time to calculate the minimum free energy for RNA secondary structure. To date, there are two variants for handling this problem: either the internal loops are bounded by a maximal size k giving a time complexity of O(n2*k2), or one uses the trick of Rune Lyngso, which makes use of the regularities of loop energies, to reduce time complexity to O(n3) without restriction. We propose a new dynamic programming algorithm for RNA secondary structure prediction by analyzing energy rules. Through only additional O(n) space, this algorithm eliminates redundant calculation in the energy calculation of internal loop with unrestricted/restricted size and reduces the time complexity of this part from O(n4) to O(n3), then the overall time complexity to O(n3).