Xu Jing-Ping

Effect of interface-roughness scattering on mobility degradation in SiGe p-MOSFETs with a high-k dielectric/SiO2 gate stack

A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer (SiO2) thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer, as well as moderate permittivities of high-k dielectrics, is highly desired to improve carriers mobility while keeping a low equivalent oxide thickness. Simulated results agree reasonably with experimental data.

Quality improvement of low-pressure chemical-vapor-deposited oxide by N2O nitridation

Quality of low-pressure chemical-vapor-deposited (LPCVD) oxide and N2O-nitrided LPCVD (LN2ON) oxide is investigated under high-field stress conditions as compared to thermal oxide. It is found that LPCVD oxide has lower midgap interface-state density Dit-m and smaller stress-induced Dit-m increase than thermal oxide, but exhibits enhanced electron trapping rate and degraded charge-to-breakdown characteristics, which, however, are significantly suppressed in LN2ON oxide, suggesting effective elimination of hydrogen-related species. Moreover, LN2ON oxide shows further improved Si/SiO2 interface due to interfacial nitrogen incorporation.

Improved interfacial and electrical properties of Ge MOS devices with ZrON/GeON dual passivation layer*

The interfacial and electrical characteristics of Ge metal-oxide-semiconductor (MOS) devices with a dual passivation layer of ZrON/GeON formed by NH 3 - or N 2 -plasma treatment are investigated. The experimental results show that the NH 3 -plasma treated sample exhibits significantly improved interfacial and electrical properties as compared to the samples with N 2 -plasma treatment and no treatment: a lower interface-state density at the midgap (1.64 × 10 11 cm -2 ·eV -1 ) and gate leakage current (9.32 × 10 -5 A/cm 2 at V fb + 1 V), a small capacitance equivalent thickness (1.11 nm) and a high k value (32). X-ray photoelectron spectroscopy is used to analyze the involved mechanisms. It is indicated that more GeON and less GeO x ( x 3 -plasma treatment than the N 2 -plasma treatment, resulting in a high-quality high- k /Ge interface, because H atoms and NH radicals in NH 3 -plasma can enhance volatilization of the unstable low- k GeO x , creating high-quality GeON passivation layer. Moreover, more nitrogen incorporation in ZrON/GeON induced by NH 3 -plasma treatment can build a stronger N barrier and thus more effectively inhibit in-diffusion of O and Ti from high- k gate dielectric and out-diffusion of Ge.

High-k gate dielectric GaAs MOS device with LaON as interlayer and NH3-plasma surface pretreatment*

High-k gate dielectric HfTiON GaAs metal-oxide–semiconductor (MOS) capacitors with LaON as interfacial passivation layer (IPL) and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither LaON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated GaAs MOS device with a stacked gate dielectric of HfTiON/LaON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, LaON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/GaAs interface.

Effect of initial linear chirp on collision characteristics of two solitons in the birefringent fibre

The collision characteristics of the orthogonally polarized solitons with initial linear frequency chirp in the linear birefringent fibre for �2 < 0 are numerically studied. It is found that initial chirp changes the threshold value of solitons to form the bound-state in the birefringent fibre. The effect of initial positive chirp on the threshold value is more obvious than that of negative chirp. In the case of � = 0.7 and initial interval 2�0 = 1.25, the two solitons are mutually bound for 0.2 � C � 1, and they do not form the bound-state for 1 � C < 0.2. Frequency shifts increase with the increase of chirp parameter C for 1 � C < 0.2, and have the oscillatory structure for C � 0.2. The effect of positive chirp on temporal FWHM is greater than that of negative chirp. The peak of temporal waveform oscillates with the propagation distance. The period and amplitude of the oscillation for the chirped case are greater than those for the unchirped case, and they vary with the increase of |C|. The peak of output temporal waveform can be controlled by changing the initial chirp.

Electrical characteristics of MOS capacitor with HfTiON gate dielectric and HfTiSiON interlayer

The paper reports that HfTiO dielectric is deposited by reactive co-sputtering of Hf and Ti targets in an Ar/O2 ambience, followed by an annealing in different gas ambiences of N2, NO and NH3 at 600°C for 2 min. Capacitance–voltage and gate-leakage properties are characterized and compared. The results indicate that the NO-annealed sample exhibits the lowest interface-state and dielectric-charge densities and best device reliability. This is attributed to the fact that nitridation can create strong Si≡≡N bonds to passivate dangling Si bonds and replace strained Si–O bonds, thus the sample forms a hardened dielectric/Si interface with high reliability.

Electrical properties and reliability of HfO2 gate-dielectric MOS capacitors with trichloroethylene surface pretreatment

Trichloroethylene (TCE) pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gate-dielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties, gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growth, the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and HCl on the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.

Preparation of Pb(Zr,Ti)O/sub 3/ ferroelectric thin films by a pulsed laser ablation technique

Ferroelectric thin films of Pb(Zr,Ti)O/sub 3/ have been fabricated on polished silicon wafers by a pulsed laser ablation technique at substrate temperature of 100-200 degrees C. The ferroelectric properties of the thin films can be greatly improved by a post-deposition laser annealing. Some factors which affect the quality of thin films were investigated. The structures of thin films were analyzed by X-ray diffraction. The Curie temperature and hysteresis loops of PZT ferroelectric thin films were measured.<<ETX>>

Electrical properties of Ge metal–oxide–semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti*

LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1 × 1011 eV−1 cm−2), gate leakage property (3.6 × 10−3 A/cm2 at V g = 1 V + V fb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.

A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric*

A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poissons equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored.