Xuanqi Chen

Morphological background detection and illumination normalization of text image with poor lighting.

In this paper, some morphological transformations are used to detect the unevenly illuminated background of text images characterized by poor lighting, and to acquire illumination normalized result. Based on morphologic Top-Hat transform, the uneven illumination normalization algorithm has been carried out, and typically verified by three procedures. The first procedure employs the information from opening based Top-Hat operator, which is a classical method. In order to optimize and perfect the classical Top-Hat transform, the second procedure, featuring the definition of multi direction illumination notion, utilizes opening by reconstruction and closing by reconstruction based on multi direction structuring elements. Finally, multi direction images are merged to the final even illumination image. The performance of the proposed algorithm is illustrated and verified through the processing of different ideal synthetic and camera collected images, with backgrounds characterized by poor lighting conditions.

Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system

Energy-efficiency is becoming increasingly important to modern computing systems with multi-/many-core architectures. Dynamic Voltage and Frequency Scaling (DVFS), as an effective low-power technique, has been widely applied to improve energy-efficiency in commercial multi-core systems. However, due to the large number of cores and growing complexity of emerging applications, it is difficult to efficiently find a globally optimized voltage/frequency assignment at runtime. In order to improve the energy-efficiency for the overall multicore system, we propose an online DVFS control strategy based on core-level Modular Reinforcement Learning (MRL) to adaptively select appropriate operating frequencies for each individual core. Instead of focusing solely on the local core conditions, MRL is able to make comprehensive decisions by considering the running-states of multiple cores without incurring exponential memory cost which is necessary in traditional Monolithic Reinforcement Learning (RL). Experimental results on various realistic applications and different system scales show that the proposed approach improves up to 28% energy-efficiency compared to the recent individual-RL approach.

Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations

Recent advances in photonics technologies have made optical interconnection network an attractive option for computing systems from high-performance computers and data centers to automobiles and cell phones. Optical interconnection network promises ultra-high bandwidth, low latency, and great energy efficiency to alleviate the inter-rack, intra-rack, intra-board, and intra-chip communication bottlenecks in multiprocessor systems. Silicon-based photonics technologies piggyback onto developed silicon fabrication processes to provide viable and cost-effective solutions. Both industry and academia have invested significant efforts to develop and commercialize optical interconnection network technologies. This paper reviews the latest progresses and provides insights into the challenges and future developments.

MOCA: an Inter/Intra-Chip Optical Network for Memory

The memory wall problem is due to the imbalanced developments and separation of processors and memories. It is becoming acute as more and more processor cores are integrated into a single chip and demand higher memory bandwidth through limited chip pins. Optical memory interconnection network (OMIN) promises high bandwidth, bandwidth density, and energy efficiency, and can potentially alleviate the memory wall problem. In this paper, we propose an optical inter/intra-chip processor-memory communication architecture, called MOCA. Experimental results and analysis show that MOCA can significantly improve system performance and energy efficiency. For example, comparing to Hybrid Memory Cube (HMC), MOCA can speedup application execution time by 2.6×, reduce communication latency by 75%, and improve energy efficiency by 3.4× for 256-core processors in 7 nm technology.

Clock Domains Cross FIFO Interface Design of Multichannel Continuous DDR2 Read and Write

In this paper, a clock domains cross FIFO interface of multichannel continuous DDR2 read and write is designed. The interface provides continuous data stream from DDR2 to 12 different channels simultaneously. Four core issues are resolved: mismatch on bit width between DDR2 user interface and the channels, data stream conversion control from DDR2 to channels, clock domains difference between DDR2 and channels, Discontinuous process of DDR2 read and write. DDR2 storage spaces are partitioned for matching data width of the DDR2 user interface and the channels, and to achieve the maximum utilization of the DDR2 memory. Via state machine, data conversion and synchronization from DDR2 to channels are implemented, and the state machine can be applied to providing continuous DDR2 data to any numbers of channels simultaneously. Cross clock domains FIFO interface goes to solve the different clock domains problem between channels and DDR2. When bank or row addresses conversion occurs, or DDR2 auto-refresh cycle comes, DDR2 cannot be read or written, leading to data interruptedly in time aspect. To solve the problem, the FIFO interface is designed followed the full-mode handshake protocol. Through the interface caching, the 12 channels can continuously read data from the DDR2 simultaneously. The final design can achieve the goal that under the fastest case, DDR2 provides 12 channels data stream simultaneously at 61.538 MHz rate at the same time, and 90.566% efficiency in the reading and writing aspects.