Xuelong Shi

Simultaneous source mask optimization (SMO)

In this paper, a method for improving the process window is described by simultaneous source mask optimization (SMO). The method optimizes the source and mask of a critical pattern by optimizing the mask in the frequency domain. The minimum image log slope (ILS) is maximized at fragmentation points in the critical pattern while simultaneously maintaining the printing fidelity. The mask optimized in the frequency domain is then converted into a chromeless phase lithography (CPL) mask. The process window with the optimized source and optimized CPL mask doubles the aerial image contrast in comparison to an attenuating PSM with source optimization only. After optimizing the mask and source for a critical pattern, the remaining parts of the full-chip design are optimized with interference mapping. Another technique for optimizing the source for a full chip is presented in which the source is optimized by using the pitch frequency of the design. From the pitch frequency, the source is optimized by solving an integral equation for the first eigenfunction in which the first eigenfunction is calculated from the sum of coherent system (SOCS) representation of the transfer cross coefficient (TCC).

Understanding the forbidden pitch and assist feature placement

Optical proximity effect is a well-known phenomenon in photolithography. Such an effect results from the structural interaction between the main feature and the neighboring features. Recent observations have shown that such structural interactions not only affect the critical dimension of the main feature at the image plane, but also the exposure latitude of the main feature. In this paper, it has been shown that the variation of the critical dimension as well as the exposure latitude of the main feature is a direct consequence of light field interference between the main feature and the neighboring features. Depending on the phase of the field produced by the neighboring features, the main feature critical dimension and exposure latitude can be improved by constructive light field interference, or degraded by destructive light field interference. The phase of the field produced by the neighboring features can be shown to be in the location where the field produced by the neighboring features can be shown to be dependent on the pitch as well as the illumination angle. For a given illumination, the forbidden pitch lies in the location where the field produced by the neighboring features interferes with the field of the main feature destructively. The theoretical analysis given here offers the tool to map out the forbidden pitch locations for any feature size and illumination conditions. More importantly, it provides the theoretical ground for illumination design in order to suppress the forbidden pitch phenomenon, and for scattering bar placement to achieve optimal performance as well.

Extending aggressive low-k1 design rule requirements for 90 and 65 nm nodes via simultaneous optimization of numerical aperture, illumination and optical proximity correction

It has been a challenge for the lithography process to meet aggressive integrated circuit design rule requirements for 90 nm and upcoming 65 nm technology nodes under low-k1 patterning constraints. The geometric design rules are largely governed by numerical aperture (NA), illumination settings, and optical proximity correction (OPC) for any resolution enhancement technique-applied mask. A set of process feasible design rule criteria is explored based on state-of-the-art microprocessor chip that contains three different types of circuit design-standard library cell (SLC), random logic (RML), and static random access memory (SRAM). The critical design rule criteria to keep higher packing density for SRAM involve: achievable minimum pitch, sufficient area of contact-landing pad, minimum line-end shortening (LES) to ensure poly end-cap and preferably optimum pitch for placement of Scattering BarTM (SB). The goal is to achieve printing of ever-smaller critical dimension (CD) with greater CD uniformity control for RML. SLC should be designed with comparable criteria to both RML and SRAM devices. Hence, the design rule constraints for CD, space, line-end, minimum pitch and SB placement for SLC cell are critically confined. Unlike traditional method of assuming a linear scaling for the design rule set, achievable design rule criteria is explored for very low k1-imaging by simultaneously optimizing NA, illumination settings and OPC (for optimum placement of SB) for a calibrated process. This is done by analyzing CD uniformity control and maximum overlapped process window for critical lines, spaces and line-ends with the respective k1 factor for three types of circuits. A feasible set of design rules for 90 nm node with k1 as low as 0.36 can be obtained using 6% attenuated phase shift mask (attPSM) with 6% exposure latitude at 400 nm of overlapped depth of focus.

Contact hole reticle optimization by using interference mapping lithography (IML)

The theory of interference mapping lithography (IML) is presented for low k1 (k1<0.4) contact hole imaging. IML with a coherent source is shown to be analogous to methods used in creating a Fresnel lens. With IML for a partially coherent source, the interference map is calculated by using the first eigenfunction of the transmission cross coefficient (TCC). From this interference map, clear 0° AFs and for clear 180° AFs are placed in the optimal location. Thus, IML is a method to place AFs via a model. From the interference map, a method for creating a CPL mask is demonstrated. Using IML, techniques to optimize a binary mask or a CPL mask are presented for maximizing the exposure latitude (EL) or depth of focus (DOF). These techniques are verified with simulation. Using IML for maximum EL, a CPL mask with 100nm (k1=0.39) contacts was created and exposed on an ASML /1100 ArF scanner using NA of 0.75 and Quasar illumination (σin=0.72, σout=0.92, span angle=20°). Measurements on the exposed wafers show that IML CPL results in printing 100nm contacts through pitch (200nm minimum pitch to isolated) with 0.45μm DOF at 10% EL.

Understanding the forbidden pitch phenomenon and assist feature placement

Optical proximity effect is a well-known phenomenon in photolithography. Such an effect results from the structural interaction between the main feature and the neighboring features. Recent observations have shown that such structural interactions not only affect the critical dimension of the main feature at the image plane, but also the exposure latitude of the main feature. In this paper, it has been shown that the variation of the critical dimension as well as the exposure latitude of the main feature is a direct consequence of light field interference between the main feature and the neighboring features. Depending on the phase of the field produced by the neighboring features, the main feature exposure latitude can be improved by constructive light field interference, or degraded by destructive light field interference. The phase of the field produced by the neighboring features can be shown to be dependent on the pitch as well as the illumination angle. For a given illumination, the forbidden pitch lies in the location where the field produced by the neighboring features interferes with the field of the main feature destructively. The theoretical analysis given here offers the tool to map out the forbidden pitch locations for any feature size and illumination conditions. More importantly, it provides the theoretical ground for illumination design in order to suppress the forbidden pitch phenomenon, and for scattering bar placement to achieve optimal performance as well.

Dipole decomposition mask design for full-chip implementation at 100-nm technology node and beyond

For cost-effective Integrated Circuit (IC) manufacturing, it is highly desirable to use Binary-Chrome Masks (BIMs) instead of Phase Shifting Masks (PSMs). For the 70nm technology node, it is of particularly appealing if Argon Fluoride (ArF) BIMs can still be used. In this paper, we demonstrate that double dipole ArF exposure together with BIMs is capable of achieving acceptable overlapped process window for printing 70nm Critical Dimension (CD) features. The main challenge of using such a technique for IC manufacturing is how to properly decompose the original mask patterns into two separate orientation masks (vertical and horizontal). To compensate for the possible two-dimensional (2D) pattern distortion due to the strong proximity effect, a novel set of

RET masks for the final frontier of optical lithography

With immersion and hyper numerical aperture (NA>1) optics apply to the ITRS 2003/4 roadmap scenario (Figure 1); it is very clear that the IC manufacturing has already stepped into the final frontier of optical lithography. Today’s advanced lithography for DRAM/Flash is operating at k1 close to 0.3. The manufacturing for leading edge logic devices does not follow too far behind. Patterning at near theoretical lithography imaging limit (k1=0.25) even with hyper NA optics, the attainable aerial image contrast is marginal at best for the critical feature. Thus, one of the key objectives for low k1 lithography is to ensure the printing performance of critical features for manufacturing. Resolution enhancement technology (RET) mask in combination with hyper NA and illumination optimization is one primary candidate to enable lithography manufacturing at very low k1 factor. The use of rule-based Scattering Bars (SB) for all types of phase-shifting masks has become the de facto OPC standard since 180nm node. Model-based SB OPC method derives from interference mapping lithography (IML) has shown impressive printing result for both clear (gate) and dark field (contact and via) mask types. There are four basic types of RET mask candidates for 65nm node, namely, alternating phase-shifting mask (altPSM), attenuated PSM (attPSM), chromeless phase lithography (CPL) PSM, and double dipole lithography (DDL) using binary chrome mask. The wafer printing performances from CPL and DDL have proven both are strong candidates for 45nm nodes. One concern for using RET masks to target 45 nm nodes is likely to be the scaling for SB dimension for 4X mask. To assist imaging effectively with high NA, SB cannot be too small in width. However, for SB to be larger than sub-resolution, they can easily cause unwanted SB printing. The other major concern is the unwanted side lobe printing. This may occur for semi-dense pitch ranges under high NA and strong off-axis-illumination (OAI). Looking ahead, for manufacturing at 45 nm and 32nm nodes, one challenge is to break through the so-called k1 barrier (0.25). Multiple exposure schemes in conjunction with RET masks is our proposed solution

Near-0.3 k1 full pitch range contact hole patterning using chromeless phase lithography (CPL)

Resolution Enhancement Techniques (RET), or low k1 imaging, has been deployed successfully to extend the resolution limits of optical lithography significantly below half-λ for todays poly gate mask in the state-of-the-art manufacturing processes. However, achieving satisfactory contact hole patterning through the full pitch range required for the 90nm and 65nm technology nodes has greatly challenged the leading process development effort. Currently, attenuated PSMs with transmission between 5% and 9% are used to enhance the resolution of dark field contact hole patterns. Using conventional illumination with a low sigma, which is the common method employed for att-PSM, limits the minimum pitch that can be resolved on the wafer. By using off-axis illumination (OAI) it is possible to image smaller pitches. However, the same attributes that enhance imaging for dense patterns severely degrade the imaging of isolated patterns. Using Chromeless Phase Lithography (CPL), sub-wavelength isolated contact patterns can be imaged using strong off-axis illumination, such as Quasar, dipole and double dipole, etc. By applying modeled sub-resolution and non-printing features, we found it is possible to achieve very high-resolution contact imaging with exceptional process latitude. Both phase shifted and non-phase shifted patterns can be much larger than sub-resolution assist features (or anti-Scattering Bars) used on dark field binary reticles (~three times larger), making the reticle pattern easier to manufacture. Using this method, sub-wavelength bright patterns on a dark field can be imaged through the full pitch range. We have shown that it is feasible to push the contact resolution limit to 0.33 k1 or smaller.

Optimizing and Enhancing Optical Systems to Meet the Low k 1 Challenge

Current roadmaps show that the semiconductor industry continues to drive the usable Rayleigh resolution towards the fundamental limit (for 50% duty cycle lines) at k1=0.25. This is being accomplished through use of various resolution enhancement technologies (RETs), extremely low aberration optics with stable platforms, and resists processes that have ever-increasing dissolution contrast and smaller diffusion lengths. This talk will give an overview of the latest optical mechanisms that can be used to improve the imaging system for low k1 resolutions. We show 3 non-photoresist techniques to measure the optical parameters of a scanner: 1) a new fast phase measurement interferometer to measure aberrations is presented with an accuracy and repeatability of <3mλ, 2) we introduce a method to measure the illumination profile of the exposing source, and 3) a measurement system to monitor scattered light is presented with correlation to other techniques using a salted pellicle experiment to create controlled scattered light. The optimization of illumination and exposure dose is presented. We show the mechanism for customizing illumination based on specific mask layers. We show how this is done and compare process windows to other more conventional modes such as annular illumination or QUASAR. The optimum design is then implemented into hardware that can give extremely high optical efficiency. We also show how system level control mechanisms can be used to field-to-field and across-field exposure to compensate for lithography errors. Examples of these errors can include reticle CD deviations, wavefront aberrations, and across-field illumination uniformity errors. CD maps, facilitated by SEM and ELM, can give the prescribed changes necessary. We present a system that interfaces to new hardware to compensate these effects by active scanner corrections.

65-nm full-chip implementation using double dipole lithography

Double Dipole Lithography (DDL) has been demonstrated to be capable of patterning complex 2D patterns. Due to inherently high aerial imaging contrast, especially for dense features, we have found that it has a very good potential to meet manufacturing requirements for the 65nm node using ArF binary chrome masks. For patterning in the k1<0.35 regime without resorting to hard phase-shift masks (PSMs), DDL is one unique Resolution Enhancement Technique (RET) which can achieve an acceptable process window. To utilize DDL for printing actual IC devices, the original design data must be decomposed into “vertical (V)” and “horizontal (H)” masks for the respective X- and Y-dipole exposures. An improved two-pass, model-based, DDL mask data processing methodology has been established. It is capable of simultaneously converting complex logic and memory mask patterns into DDL compatible mask layout. To maximize the overlapped process window area, we have previously shown that the pattern-shielding algorithm must be intelligently applied together with both Scattering Bars (SBs) and model-based OPC (MOPC). Due to double exposures, stray light must be well-controlled to ensure uniform printing across the entire chip. One solution to minimize stray light is to apply large patches of solid chrome in open areas to reduce the background transmission during exposure. Unfortunately, this is not feasible for a typical clear-field poly gate masks to be patterned by a positive resist process. In this work, we report a production-worthy DDL mask pattern decomposition scheme for full-chip application. A new generation of DDL technology reticle set has been developed to verify the printing performance. Shielding is a critical part of the DDL. An innovative shielding scheme has been developed to protect the critical features and minimize the impact of stray light during double exposure.