Xuewu Li

A novel configurable boundary-scan circuit design of SRAM-based FPGA

This paper presents a novel configurable boundary-scan circuit (CBSC) of SRAM-based field programmable gate array (FPGA). The embedded SRAM cells of FPGA have been used to modify the original structure of boundary-scan circuit (BSC). Users only need to change the data stored in the embedded SRAM cell during the configuration of the FPGA chip. In this way, the boundary-scan chain can be configured to any desired length. Compared with the original structure of BSC, this circuit using 0.25µm CMOS process can be part of a standard digital cell library and has been used in the BQV series FPGAs of BMTI.

A configurable fault-tolerant glitch-free clock switching circuit

This paper has analyzed the conventional glitch-free clock multiplexers. An improved glitch-free clock switching circuit is proposed, which introduces fault-tolerant function that is able to switch away from a failed clock, and adds configurable bit that controls the switching clock edge. It is quite suitable used as a global clock multiplexer in FPGA. This switching circuit achieves three basic functions: clock select, clock enable, and clock disable. As the configurable low-level triggered latch is proposed, switching time is reduced by 1/3 compared to the double D flip-flops type clock multiplexer. This proposed switching circuit operates at 100 MHz with 17uW power consumption using TSMC 0.13um CMOS process parameters with a supply voltage of 1.5V.

SEU sensitivity evaluation of JTAG circuit used for SRAM-based FPGA

SRAM-based FPGA has become a core device in space application. However, based on CMOS technology, SRAM-based FPGA is sensitive for SEU effect. JTAG circuit is a significant module of SRAM-based FPGA, executing boundary-scan test and global configuration function. SEU effect can result in function disturbance of JTAG circuit. To adopt reasonable harden strategies for JTAG circuit, the paper puts forward an experimental scheme to evaluate the sensitivity of each module for SEU. Simulation results illustrate that the sensitivity of TAP Controller module is highest, 60% or more, compared with other modules. Finally, the paper proposes corresponding harden measures for sensitive module.

300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application (Abstract Only)

SRAM-based FPGAs have been widely used in space engineering. However, the configuration memory in SRAM-based FPGA is susceptible to the single event effects (SEE). It can disrupt the communication or control functions of the spacecraft. To mitigate SEE effects of the SRAM-based FPGAs used in space radiation environment, Beijing Microelectronics Technology Institute (BMTI) developed a 300 thousand gates Single Event Effect hardened SRAM-based FPGA -- BQVR300RH. The BQVR300RH employs Radiation Harden by Design (RHBD) technique. Hardened standard cell library based on Adaptive SRAM (ASRAM) structure is established. For especially sensitive and important resource, other assistant techniques are also adopted. The experiment results show that the BQVR300RH improved the anti-SEU characteristic a lot, compared with Xilinx 300 thousand gates space-grade SRAM-based FPGA (XQVR300). The SEU threshold of BQVR300RH is 19.06 MeV⋅cm2/mg. The anti-SEU characteristic improves three orders of magnitude than XQVR300. The improvement of anti-SEU behavior expands the usage of SRAM-based FPGA in aerospace applications. Currently, BQVR300RH has been used in space field in China.

A dynamically reconfigurable multi-functional PLL for SRAM-based FPGA in 65nm CMOS technology

Phase-locked loops (PLL) have been widely utilized in FPGA as an important module for clock management. PLL with dynamic reconfiguration capability is always welcomed in FPGA design as it is able to decrease power consumption and simultaneously improve flexibility. In this paper, a multi-functional PLL with dynamic reconfiguration capability for 65nm SRAM-based FPGA is proposed. Firstly, configurable charge pump and loop filter are utilized to optimize the loop bandwidth. Secondly, the PLL incorporates a VCO with dual control voltages to accelerate the adjustment of oscillation frequency. Thirdly, three configurable dividers are presented for flexible frequency synthesis. Lastly, a configuration block with dynamic reconfiguration function is proposed. Simulation results demonstrate that the proposed multi-functional PLL can output clocks with configurable division ratio, phase shift and duty cycle. The PLL can also be dynamically reconfigured without affecting other parts’ running or halting the FPGA device.Phase-locked loops (PLL) have been widely utilized in FPGA as an important module for clock management. PLL with dynamic reconfiguration capability is always welcomed in FPGA design as it is able to decrease power consumption and simultaneously improve flexibility. In this paper, a multi-functional PLL with dynamic reconfiguration capability for 65nm SRAM-based FPGA is proposed. Firstly, configurable charge pump and loop filter are utilized to optimize the loop bandwidth. Secondly, the PLL incorporates a VCO with dual control voltages to accelerate the adjustment of oscillation frequency. Thirdly, three configurable dividers are presented for flexible frequency synthesis. Lastly, a configuration block with dynamic reconfiguration function is proposed. Simulation results demonstrate that the proposed multi-functional PLL can output clocks with configurable division ratio, phase shift and duty cycle. The PLL can also be dynamically reconfigured without affecting other parts’ running or halting the FPGA device.

A Charge Pump PLL with Fast-locking Strategies Embedded in FPGA in 65nm CMOS Technology

Phase-locked loops (PLL) have been widely utilized in FPGA as an important module for clock management. In this paper, a charge pump PLL with fast-locking strategies embedded in 65nm FPGA is proposed. Firstly, a configurable prestart circuit is utilized to initialize the operation state of PLL. Secondly, a bandwidth switch strategy is proposed to manage the contradiction between locking speed and noise performance. Thirdly, the PLL incorporates a VCO with dual control voltages to accelerate the adjustment of oscillation frequency. Simulation results demonstrate that the proposed fast-locking PLL can lock in 2.20μs with a reference clock of 50MHz and an output clock of 1GHz, acquiring an 81.5% reduction in locking time compared to traditional PLL.

Analyzing the Single Event Upset Sensitivity of Digital Clock Manager in Virtex-5 FPGA

SRAM-based FPGAs(Field Programmable Logic Arrays) always suffer SEU(Single Event Upset) in space applications, causing bit-flips in configuration memory. Especially, the trend of compression of semiconductor feature size increases the FPGAs vulnerability. In order to validate reliability and explore weakness of FPGA-based circuits, many testing mechanisms have been proposed. Previous studies have confirmed that SEU occurs in different on-chip resources will result in different consequences. And most circumstances are about logic altering and routing error of local regions. However, when configuration bits of DCM (Digital Clock Manager) flip, the clock outputs confusion is very likely to lead a large-scale circuit fault. Currently, few papers or reports have studied SEU of DCM. This paper presents a methodology to analyze DCMs SEU sensitivity. A process of bitstream parsing is employed first to find out the correspondence between DCM block and its configuration bits. Then SEU emulation in DCM is carried out by bitstream-based fault injection. Experimental results show that each clock output of DCM has its own, different degree of sensitivity. According analyzing the number and location of the output-specific fault bits, a general sensitive-bit distribution map is drawn. In addition, certain DCM attribute-accessing bits also be identified through fixed-point fault injection. This awareness will help to study DCM SEU mitigations or radiation hardening strategies in future work.

A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only)

The programmability of an FPGA poses a number of challenges when it comes to complete and comprehensive testing of the FPGA itself. A large number of configurations must be downloaded into the FPGA to test the programmable sources. A great many methods were proposed to reduce the number of configurations to minimize the test time, but few of papers were focus on reducing single configuration time. This paper proposes a novel method to reduce more than 30% of the total configuration time based on partial reconfiguration technology and sorting algorithm. This method is implemented on a series of SRAM-based FPGAs. The experimental result shows that this method reduces 30%-45% of the total configuration time and can be generally applied to all SRAM-based FPGAs currently.

A programmable DCO-based digital clock multiplier and divider

A programmable DCO-based digital clock multiplier and divider is presented in this paper. The multiplication ratio M and division ratio D can be programmed from 2 to 32, and 1 to 32, respectively. The proposed architecture uses a coarse tune circuit to reduce the lock time and a phase maintenance mechanism to overcome the process, voltage, and temperature (PVT) variations. With a new switching control scheme is employed in the digitally controlled oscillator (DCO), the clock generator achieves similar jitter performance as conventional MDLL. The frequency range of the input and output clock are 1 ~ 270 MHz and 15 ~ 400 MHz, respectively. This clock generator is implemented in TSMC 0.13-μm CMOS technology. The measured cycle-to-cycle timing jitter at 400 MHz is 8.4ps (rms) and 117 ps (pk-pk) with a power consumption of 24 mW at a 1.5-V power supply.

A novel application of FPGA-based partial dynamic reconfiguration system with CBSC

Dynamic reconfiguration system allows us to dynamically allocate hardware resources as needed by particular applications. This paper focuses on the application of FPGA-based partial dynamic reconfiguration system (PDRS) with configurable boundary-scan circuit (CBSC), which can be used in many different fields, especially in the military and aerospace fields. Generally speaking, if an important function such as key encryption needs to be changed in a PDRS operating on a high security system, the corresponding logic resources need to be verified and tested again before being reconfigured. By making use of the CBSC technology, the effective speed of fault diagnosis for target FPGA will be accelerated, and the reliability of the PDRS will be improved. A PCB-level platform which can be used as a common platform for SRAM-based FPGA has been designed with BQV series FPGA of BMTI in this paper. Verified with test vectors of BQV600, the complete testing time for logic resources of BQV600 has been decreased significantly.