Xuming Zou

Interface Engineering for High‐Performance Top‐Gated MoS2 Field‐Effect Transistors

In recent years, due to the intriguing electrical and optical characteristics, two dimensional layered transition metal dichalcogenides such as MoS2 have attracted tremendous research attention. In a distinct contrast to the bandgap issue of graphene, MoS2 is semiconducting with a satisfied thickness-dependent bandgap of 1.2 to 1.8 eV, which can enable lots of fascinating device applications. However, until now, majority of the efforts have been focused on the integration of MoS2 devices in the back- or dual-gated geometry due to the difficulty of compact and conformal top-gated dielectric deposition directly onto the 2-D channel for the realization of high-performance top-gated FETs. In this regard, interface or dielectric engineering is an important step towards the practical implementation of MoS2 devices with the optimized performance.

Single InAs Nanowire Room-Temperature Near-Infrared Photodetectors

Here we report InAs nanowire (NW) near-infrared photodetectors having a detection wavelength up to ∼1.5 μm. The single InAs NW photodetectors displayed minimum hysteresis with a high Ion/Ioff ratio of 10(5). At room temperature, the Schottky-Ohmic contacted photodetectors had an external photoresponsivity of ∼5.3 × 10(3) AW(-1), which is ∼300% larger than that of Ohmic-Ohmic contacted detectors (∼1.9 × 10(3) AW(-1)). A large enhancement in photoresponsivity (∼300%) had also been achieved in metal Au-cluster-decorated InAs NW photodetectors due to the formation of Schottky junctions at the InAs/Au cluster contacts. The photocurrent decreased when the photodetectors were exposed to ambient atmosphere because of the high surface electron concentration and rich surface defect states in InAs NWs. A theoretical model based on charge transfer and energy band change is proposed to explain this observed performance. To suppress the negative effects of surface defect states and atmospheric molecules, new InAs NW photodetectors with a half-wrapped top-gate had been fabricated by using 10 nm HfO2 as the top-gate dielectric.

High Mobility MoS2 Transistor with Low Schottky Barrier Contact by Using Atomic Thick h-BN as a Tunneling Layer.

High-performance MoS2 transistors are developed using atomic hexagonal boron nitride as a tunneling layer to reduce the Schottky barrier and achieve low contact resistance between metal and MoS2 . Benefiting from the ultrathin tunneling layer within 0.6 nm, the Schottky barrier is significantly reduced from 158 to 31 meV with small tunneling resistance.

Controllable Electrical Properties of Metal-Doped In2O3 Nanowires for High-Performance Enhancement-Mode Transistors

In recent years, In(2)O(3) nanowires (NWs) have been widely explored in many technological areas due to their excellent electrical and optical properties; however, most of these devices are based on In(2)O(3) NW field-effect transistors (FETs) operating in the depletion mode, which induces relatively higher power consumption and fancier circuit integration design. Here, n-type enhancement-mode In(2)O(3) NW FETs are successfully fabricated by doping different metal elements (Mg, Al, and Ga) in the NW channels. Importantly, the resulting threshold voltage can be effectively modulated through varying the metal (Mg, Ga, and Al) content in the NWs. A series of scaling effects in the mobility, transconductance, threshold voltage, and source-drain current with respect to the device channel length are also observed. Specifically, a small gate delay time (0.01 ns) and high on-current density (0.9 mA/μm) are obtained at 300 nm channel length. Furthermore, Mg-doped In(2)O(3) NWs are then employed to fabricate NW parallel array FETs with a high saturation current (0.5 mA), on/off ratio (>10(9)), and field-effect mobility (110 cm(2)/V·s), while the subthreshold slope and threshold voltage do not show any significant changes. All of these results indicate the great potency for metal-doped In(2)O(3) NWs used in the low-power, high-performance thin-film transistors.

Floating Gate Memory‐based Monolayer MoS2 Transistor with Metal Nanocrystals Embedded in the Gate Dielectrics

Charge trapping layers are formed from different metallic nanocrystals in MoS2 -based nanocrystal floating gate memory cells in a process compatible with existing fabrication technologies. The memory cells with Au nanocrystals exhibit impressive performance with a large memory window of 10 V, a high program/erase ratio of approximately 10(5) and a long retention time of 10 years.

Scalable Integration of Indium Zinc Oxide/Photosensitive‐Nanowire Composite Thin‐Film Transistors for Transparent Multicolor Photodetectors Array

By incorporating crystalline photosensitive nanowires (NWs), an amorphous InZnO (a-IZO) thin film is designed to be sensitive to the primary colors of light via a facile sol-gel approach. The mobility is also improved. The composite devices leverage the advantages of the transparency of a-IZO with the photosensitivity of CdS NWs.

Dielectric Engineering of a Boron Nitride/Hafnium Oxide Heterostructure for High‐Performance 2D Field Effect Transistors

A unique design of a hexagonal boron nitride (h-BN)/HfO2 dielectric heterostructure stack is demonstrated, with few-layer h-BN to alleviate the surface optical phonon scattering, followed by high-κ HfO2 deposition to suppress Coulombic impurity scattering so that high-performance top-gated two-dimensional semiconductor transistors are achieved. Furthermore, this dielectric stack can also be extended to GaN-based transistors to enhance their performance.

Integration of High-k Oxide on MoS2 by Using Ozone Pretreatment for High-Performance MoS2 Top-Gated Transistor with Thickness-Dependent Carrier Scattering Investigation

A top-gated MoS2 transistor with 6 nm thick HfO2 is fabricated using an ozone pretreatment. The influence to the top-gated mobility brought about by the deposition of HfO2 is studied statistically, for the first time. The top-gated mobility is suppressed by the deposition of HfO2 , and multilayered samples are less susceptible than monolayer ones.

Low Interface Trap Densities and Enhanced Performance of AlGaN/GaN MOS High- Electron Mobility Transistors Using Thermal Oxidized Y 2 O 3 Interlayer

AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with Y₂O₃ interlayer have been investigated to improve the interface quality. With the HfO₂/Y₂O₃ stack gate dielectrics, the devices show a saturated drain current density of up to ~943 mA/mm. Meanwhile, the pulsed Id-Vg measurement indicates interface traps are as low as 5.2 × 10¹¹ cm^-2, and the pulsed-IV measurement exhibits great resistance to current collapse. Furthermore, the devices also present good reliability under negative bias stress. Therefore, the interface engineering based on Y₂O₃ has a potential to open up a new avenue to high-performance AlGaN/GaN MOS-HEMTs.

Side-Gated In2O3 Nanowire Ferroelectric FETs for High-Performance Nonvolatile Memory Applications

A new type of ferroelectric FET based on the single nanowire is demonstrated. The design of the side‐gated architecture not only simplifies the manufacturing process but also avoids any postdeposition damage to the organic ferroelectric film. The devices exhibit excellent performances for nonvolatile memory applications, and the memory hysteresis can be effectively modulated by adjusting the side‐gate geometries.