Xunwei Wu

A new design of double edge triggered flip-flops

The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 /spl mu/ technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time, and higher maximum data rate compared to other existing CMOS DET flip-flops. By simulating and comparing the proposed DET flip-flop with the traditional single-edge-triggered (SET) flip-flop, it is shown that the proposed DET flip-flop reduces power dissipation by half while keeping the same date rate.

Design of ternary CMOS circuits based on transmission function theory

This paper presents threshold comparison operation, transmission operation and union operation which can be used to describe the function of MOS transistors in a pass-transistor network. The relative properties and circuit realizations of these operations, and the transmission function expression by use of these operations are discussed. A transmission function theory suitable to CMOS network synthesis is proposed. This paper also discusses the simplification of ternary functions and proposes minimized design of some basic ternary CMOS circuits. The computer simulation using SPICE2G5 has confirmed that these circuits have desirable DC transfer characteristics.

A note on the relationship between signal probability and switching activity

In current probability calculation algorithms for power estimation, switching activity E/sub SW/ of a node is calculated from its signal probability p by the following simple relation: E/sub SW/=2p(1-p). It is generally understood that this simple relationship holds under the temporal independence assumption for the node. This paper however shows that the above equation also gives the expected value of the transition activity in any sequence that satisfies the given signal probability (averaged over all such sequences). Therefore, this equation can be used to calculate the switching activity under more general conditions than previously thought.

Ternary CMOS sequential circuits

Threshold comparison, transmission, and union operations are discussed and used as the basis of a logic design procedure for CMOS ternary circuits. Some basic CMOS ternary circuits are used to design CMOS ternary flip-flops (tri-flops) such as the ternary latch and various master-slave tri-flops. These tri-flops have two additional binary inverse outputs with a fixed threshold. A modulo-9 up counter is presented as an example of sequential circuit design using these tri-flops.<<ETX>>

Low-power sequential circuit design using T flip-flops

This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by using T flip-flops. The unwanted triggering action of the master clock to flip-flops can be isolated during T = 0. An example design of a decimal counter demonstrates the large power saving and improved performance of the resulting circuit.

Design of the one-zero-hot controller

This paper proposes the one-zero-hot controller for digital circuit design, based on the traditional one-hot controller but making use of the all-clear condition of the state flip-flops. We introduce a new form of K-map for mutually exclusive variables, and show it to be useful for synthesizing functions based on the one-zero-hot controller. In a discussion of practical design examples, we show that the one-zero-hot controller has a simpler structure and achieves self-correction more easily than the conventional one-hot controller.

Theory of differential current switches and logic design of ternary ECL circuits at switch level

Abstract Starting from the viewpoint that the switch states and signal values in a digital circuit should be described separately by two different kinds of variable, the interaction between the switching element and signal in multi-valued ECL circuits is analysed and two types of connection operations, threshold switching operation and current switching operation, are proposed. The properties and circuit realizations of these new operations are discussed and the theory of differential current switches applicable to ECL circuits is established. Examples of basic ternary ECL circuits confirm that this theory can effectively guide the logic design of ternary ECL circuits at switch level. The circuits are verified by using the SPICE II program. They have the same logic level difference and transient characteristic as binary ECL circuits. Since the multi-valued ECL circuit uses only one set of power supply and can set several threshold values by using reference levels, it can be fabricated using conventional E...

Design of ternary nMOS circuits based on the theory of clipping voltage switches

The theory of clipping voltage switches suitable for ternary nMOS circuits is proposed, assuming that the switching states of the elements and signals in a circuit should be described separately by using switching variables and signal variables. Threshold comparison operations and voltage-clipping operation are introduced, which can reflect the working principle of nMOS circuits. Their relative properties and the expressions of the logic functions are discussed. Based on the theory some basic ternary nMOS circuits are designed and simulated. Simulation results using SPICE show that these circuits have correct logic functions and desirable DC and transient characteristics.

Abacus logic and its CMOS circuits

Decimal codes are proposed for biquinary (‘2–5’) mixed-valued signals, i.e. abacus logic, and a procedure for designing CMOS quinary circuits based on transmission function theory. Some 2–5 mixed-valued circuits for both combinational and sequential logic are designed and simulated by using SPICE2G5. Using a multiple ion implantation technique, we may integrate both the binary and quinary cells in the above circuits on the same chip. In comparison with traditional BCD binary circuits, they have several advantages, such as fewer connections, simpler construction and no redundancy.

The theory of clipping voltage-switches and design of quaternary nMOS circuits

A theory of clipping voltage-switches suitable to quaternary nMOS circuits is proposed. It is based on the viewpoint that switching states of elements and signals in a circuit should be described separately by using switching variables and signal variables. Threshold comparison operations and voltage-clipping operation that can reflect the working principle of nMOS circuits are introduced. Their relative properties and logic-function expressions are discussed. Some basic quaternary nMOS circuits are designed in order to demonstrate the procedure.<<ETX>>