Yang Zhijia

Fieldbus interoperation technologies

This paper discusses several interoperation technologies in fieldbus systems. Based on studying of several popular fieldbus standards, analyzed the key technologies of interoperation between homogeneous protocols: standardized application layer logic structure and device description. In order to fit different fieldbus interoperation demand between heterogeneous protocols, two types of gateways are classified: protocol-conversion-type gateway and bridge-type gateway. Their principles, characteristics, application areas and development steps are analyzed as well. With the introduction of OPC technologies, elaborates the methods to realize interoperation between multi-protocols. The limitations are also analyzed in detail and some solutions are also provided to overcome their limitations.

Design and implementation of DFT strategy for an industrial communications and control SoC

With the development of microelectronics technology, IC has come into SoC age. At the same time, the increasing complexity of SoC design presents the test some challenging problems, such as IP, system integration, test strategy, and so on. A system level DFT solution for SoC is presented through a real life case (FF_SoC, 0.18 mu m, million gates chip). The SoC architecture is centered around ARM processor in combination with SRAM, PLL, uart, GPIO, watchdog timer, memory controller, real time clock, etc. The most important IP core is FFH1, which is a Foundation Fieldbus communications and control IP core designed by our team. In this paper we presented a structural and systematic DFT approach for SoCs.

Joint design of signal detection, demodulation classification, channel estimation and automatic gain control for multi speed HART

Traditionally, signal detection, demodulation classification, channel estimation and automatic gain control are designed separately and stabilization of those functions takes lots of symbols. In this paper, we propose a joint design of all those functions for multi-speed HART, which can adaptively demodulate HART FSK and HART C8PSK signals. According to the characteristics of HART channel and HART preamble, we employ sliding windowed DFT to estimate the power spectrum of HART preamble signal. Spectrum leakage and barrier effect, which are side effects of widowed DFT, are employed. In order to estimate the power at certain frequency lines fast and alleviate the interference of noise, we employ variable coefficient low pass filer. Simulations have shown that joint design of those functions can converge fast and work very well in low SNR.

Backward compatible receiver structure for C8PSK HART

This paper presents a low-complexity C8PSK HART receiver structure that can adaptively demodulate input signal modulated in non-coherent HART FSK or coherent HART C8PSK. Spectrum leakage and barrier effect, which are defects of windowed DFT when used to analyze signal spectrum, are employed to perfectly solve both problems of channel estimation and signal identification. In order to lower power consumption of the receiver, a novel algorithm is developed for HART FSK demodulation, reusing the resource of HART C8PSK demodulator. Simulations have shown that the proposed structure can work very well in low SNR.