Yanhong Wu

Development of three-dimensional multichip module based on embedded substrate with multiple interconnections

A new type of 3D multichip module (3D-MCM) for wireless sensor network was developed based on a kind of embedded FR-4 substrate for the wireless sensor network, in which FCOB (flip-chip on board), COB (chip on board), BGA (ball grid array) technologies, wirebonding and flip-chip interconnection technologies were combined together. The PBGA device and bare die were hybrid-integrated on the embedded multi-layer FR-4 substrate. By solder ball placement and reflow the BGA was formed at the bottom of 3D-MCM, and solder balls with different melting points were used for initial and final vertical interconnections for the sake of compatibility of all levels interconnections of BGA by reflow soldering. The application of embedded substrate solved the problem that the top surface of the encapsulated chip overtops the solder balls in the condition that the chip was assembled in the same side of substrate with BGA. The thermal management was conducted and the thermal related reliability of 3D-MCM were simulated and evaluated respectively. This kind of packaging structure satisfies the electrical performance and thermal requirement, and meets the challenge of minimization, high reliability and low cost of the package design for the wireless network.

Fabrication of Submicron Beams with Galvanic Etch Stop for Si in TMAH

A novel method has been developed to fabricate submicron beams with galvanic etch stop for Si in TMAH. The different Au:Si area ratios before and after the release of the beams are used to trigger the galvanic etch stop to fabricate submicron single crystal Si beams in standard Si wafers. Before the beams are released from the substrate, the Au electrodes are connected to the substrate electrically. The Au:Si area ratios are much smaller than the threshold value. TMAH etches the Si wafers. After the beams are fully released, they are mechanically supported by the Au wires, which also serve as the galvanic etch stop cathodes. The Au:Si area ratios are much larger than the threshold value. The beams are protected by galvanic etch stop. The thicknesses of the beams are determined by shallow dry etching before TMAH etching. A 530 nm thick beam was fabricated in standard (111) wafers. Experiments showed that the beam thicknesses did not change with over etching, even if the SiO2 layers on the surface of the beams were stripped.

Fabrication of z-axis accelerometer with galvanic etch stop and antifuse isolation

This paper reports a release-after-package process to fabricate a fully symmetrical sandwich z-axis accelerometer with galvanic etch stop, which employs antifuse isolation to suppress the leakage current during etching. The sandwich structure is composed of three silicon layers. The suspension beams and the electrodes are made on the top and bottom layer. The proofmass and supporting rim are made on the middle layer. The structure is formed and released by galvanic etch stop after partially packaging to increase the yield. As the leakage current may induce unwanted etch stop of sacrificial area, antifuses are used to connect the beams and mass. The antifuses are kept off-state during TMAH etching, so that the middle layer is selectively etched to form the mass while the top and bottom layers are protected by galvanic cell. After the structure is released, the antifuse is breakdown to on-state to connect the beams and mass electrically. Two structures have been fabricated with the technique.

Design, fabrication of through silicon vias based on suspended photoresist thin film and its application in silicon interposer

This paper presents a novel fabrication method of through silicon vias (TSVs) based on suspended photoresist thin film. The AZ5214 photoresist thin film is self-assembled on the deionized (DI) water surface, then the film is transferred onto the wafer surface and patterned by photolithography to form the cover plates on the through-vias. After a Cu seed layer is deposited and the photoresist film is chemically removed, the through-vias are filled by Cu electroplating. The process steps, characterization and the feasibility are analyzed in our experiment. According to this approach, one of its applications in silicon interposer is provided and the processes are discussed.