Yao-Tsung Huang

CMOS Dual-Work-Function Engineering by Using Implanted Ni-FUSI

For the first time, a simple CMOS fully silicided (FUSI) process achieving n/pMOS band-edge work function was demonstrated, which is fully compatible with conventional CMOS process. Dual-work-function CMOS FUSI, with a wide range of 800 mV, was achieved by implantation of Yb into the poly of the nMOS gate (4.1-eV work function) and Ga into the poly of the pMOS gate (4.9-eV work function), respectively. The placement of the tuning elements at the metal/dielectric interface was engineered with the thermal budget, as well as the implant dose and species.

Theoretical and experimental investigation of valence band offsets for direct silicon bond hybrid orientation technology

Direct silicon bonding (DSB) for hybrid orientation technology has recently generated a lot of interest due to the significant performance enhancements reported for p-channel metal oxide semiconductor devices fabricated on alternative substrate orientations. This letter reports on the experimental observation and density functional theory (DFT) based theoretical prediction of a valence band offset between the (100) and (110) silicon surfaces directly bonded to each other. This constitutes a different type of junction created by the presence of two different surface orientations in close proximity to each other and not by doping or material variations. Experimentally, this band offset was observed as an asymmetry in the forward and reverse current-voltage characteristics of a two terminal device designed to flow a current across the DSB interface. Further, the valence band offset obtained from DFT simulations was used in a conventional device simulator (TAURUS-MEDICI) to simulate the behavior of this struc...

Amorphization and Templated Recrystallization (ATR) Study for Hybrid Orientation Technology (HOT) using Direct Silicon Bond (DSB) Substrates

The use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides promising opportunities for easier migration of bulk CMOS designs to higher performance materials. In this work, the integration of shallow-trench-isolation (STI) after amorphization and templated recrystallization (ATR) scheme for converting surface orientation from (110) to (100) was investigated. By optimizing the trade-off between ATR-induced triangular morphology and DSB layer thickness, a 3X holes mobility improvement and 36% drive current gain were achieved for PMOSFETs fabricated on (110) plane using DSB-HOT. In addition, un-loaded ring oscillators fabricated using DSB substrates show a 38% improvement compared with control CMOS on (100) wafers.

Efficient Transistor Optimization with Stress Enhanced Notch-gate Technology for sub-90nm CMOSFET

A simple and efficient strained engineering was reported, by implementing a notch-gate into high tensile-stress CESL (contact etch stop layer) process. Low process changes were utilized to modulate channel stress and implant profile for generating enhanced performance without any extra process step needed. Compared to conventional vertical-gate CMOSFET with an additional offset spacer, device with notch-gate as self-aligned offset spacer possess lower parasitic capacitance and shows extra 7% nMOSFET ION enhancement due to stress CESL more approached to channel center region, enhancing channel carrier mobility efficiently. For pMOSFET, even with inappropriate effect by tensile stress, extra 3% ION enhancement due to optimal channel profile by halo implantation through notch-gate structure.

Junction Passivation for Direct Silicon Bond Hybrid Orientation Technology

Direct silicon bonding (DSB) for hybrid orientation technology has recently generated a lot of interest due to the significant performance enhancements reported for PMOS devices that are fabricated on alternative substrate orientations. Significantly higher leakage was observed for P+/N diodes if the junction depletion region was located close to the interface between the (110) and (100) Si surfaces. Hydrogen and fluorine passivation of this interface by ion implantation resulted in an order of magnitude improvement in the reverse leakage. In this brief, the experiments that performed using several dose levels of H2, F, and N implants are described. Electrical characterization data for reverse leakage, forward current, and ideality factors are presented in the form of cumulative probability plots, from which it is concluded that H and F passivation by ion implantation consistently provides a significant improvement in junction leakage, as compared to an unimplanted DSB wafer. An increase in the forward resistance was observed due to the implants, as compared to bulk Si (100) control samples.

Comparison and analysis of Wuding and avian chicken skeletal muscle satellite cells

Chicken skeletal muscle satellite cells are located between the basement membrane and the sarcolemma of mature muscle fibers. Avian broilers have been genetically selected based on their high growth velocity and large muscle mass. The Wuding chicken is a famous local chicken in Yunnan Province that undergoes non-selection breeding and is slow growing. In this study, we aimed to explore differences in the proliferation and differentiation properties of satellite cells isolated from the two chicken breeds. Using immunofluorescence, hematoxylin-eosin staining and real-time polymerase chain reaction analysis, we analyzed the in vitro characteristics of proliferating and differentiating satellite cells isolated from the two chicken breeds. The growth curve of satellite cells was S-shaped, and cells from Wuding chickens entered the logarithmic phase and plateau phase 1 day later than those from Avian chicken. The results also showed that the two skeletal muscle satellite cell lines were positive for Pax7, MyoD and IGF-1. The expression of Pax7 followed a downward trend, whereas that of MyoD and IGF-1 first increased and subsequently decreased in cells isolated from the two chickens. These data indicated that the skeletal muscle satellite cells of Avian chicken grow and differentiate faster than did those of Wuding chickens. We suggest that the methods of breeding selection applied to these breeds regulate the characteristics of skeletal muscle satellite cells to influence muscle growth.

Extra Bonus on Transistor Optimization with Stress Enhanced Notched-Gate Technology for Sub-90 nm Complementary Metal Oxide Semiconductor Field Effect Transistor

A simple and efficient strain engineering technique for integrating the tensile-stress contact etch stop layer (CESL) process to a notch gate has been reported in detail. The strain engineering technique utilizes slight process modifications to modulate the channel stress and implantation profile for the enhancement of performance without adding any extra process steps. Compared with the conventional vertical-gate complementary metal oxide semiconductor field effect transistor (CMOSFET) with an offset spacer, a device with a notch gate as a self-aligned offset spacer achieves an extra 7% NMOS ION enhancement. The enhancement comes from the larger channel stress induced by the tensile-stress CESL on the notch gate, and is confirmed by technology computer aided design (TCAD) simulation. Moreover, fewer interface defects (Dit) and parasitic capacitances were obtained for the notch-gate samples.

Myostatin mRNA expression and its association with body weight and carcass traits in Yunnan Wuding chicken.

Myostatin (MSTN) is expressed in the myotome and developing skeletal muscles, and acts to regulate the number of muscle fibers. Wuding chicken large body, developed muscle, high disease resistance, and tender, delicious meat, and are not selected for fast growth. Broiler chickens (Avian broiler) are selected for fast growth and have a large body size and high muscle mass. Here, 240 one-day-old chickens (120 Wuding chickens and 120 broilers) were examined. Twenty chickens from each breed were sacrificed at days 1, 30, 60, 90, 120, and 150. Breast and leg muscle samples were collected within 20 min of sacrifice to investigate the effects of MSTN gene expression on growth performance and carcass traits. Body weight, carcass traits, and skeletal muscle mass in Wuding chickens were significantly (P < 0.05) lower than those in broiler chickens at all time points. Breast muscle MSTN mRNA was lower in Wuding chickens than in broilers before day 30 (P < 0.05). After day 30, breast muscle MSTN expression was higher in Wuding chicken than in broilers (P < 0.05). Leg muscle MSTN mRNA expression was higher in Wuding chicken than in broilers at all ages except for day 60 (P < 0.05). Correlation analysis revealed that breast muscle MSTN expression has a greater effect in slow growing Wuding chickens than in the fast growing broilers. In contract, leg muscle MSTN mRNA level has a greater effect in broilers than in Wuding chickens. MSTN regulates growth performance and carcass traits in chickens.

Multi-Gate MOSFETs with Dual Contact Etch Stop Liner Stressors on Tensile Metal Gate and Strained Silicon on Insulator (sSOI)

This paper describes a comprehensive study of the impact of tCESL (tensile Contact Etch Stop Liner) and cCESL (compressive Contact Etch Stop Liner) on tensile metal gate MuGFET with SOI and globally strained SOI (sSOI) substrates. We have demonstrated that tCESL and cCESL can be effectively used on MuGFETs to provide performance gain. Since tCESL and cCESL affect NMOS and PMOS mobilities in the opposite directions, dual stress liner technology with high-stress cCESL is needed for optimal CMOS MuGFET performance.

Extra Bonus on Transistor Optimization with Stress Enhanced Notch-gate Technology for sub-90nm CMOSFET

A simple and efficient strained engineering was reported, by implementing a notch-gate into high tensile-stress CESL (contact etch stop layer) process. Low process changes were utilized to modulate channel stress and implant profile for generating enhanced performance without any extra process step needed. Compared to conventional vertical-gate CMOSFET with an additional offset spacer, device with notch-gate as self-aligned offset spacer possess lower parasitic capacitance and shows extra 7% nMOSFET ION enhancement due to stress CESL more approached to channel center region, enhancing channel carrier mobility efficiently. For pMOSFET, even with inappropriate effect by tensile stress, extra 3% ION enhancement due to optimal channel profile by halo implantation through notch-gate structure. Introduction Strained engineering has been extensively implemented for device performance enhancement since 90nm generation and beyond. The most popular process is high tensile-stress CESL. It not only can improve nMOS ION obviously [1], but also can fully compatible with conventional CMOS process. On the other hand, SiXGeY in source/drain region can improve pMOS ION significantly but many challenges for production; such as: geometry effect, quality of epitaxy, and extra litho step [2]. Notch-gate is a good method to reduce the overlap capacitance between gate to source/drain, and optimize the channel profile by halo implantation through this notch-gate structure to improve the device’s SCE [3]; moreover, higher channel stress induced by CESL through a notch-gate edge can approach device’s channel center effectively, further improving device channel mobility especially for nMOSFET. Therefore, integrating a notch-gate with the high tensile-stress CESL is an efficient and simple method to obtain higher channel mobility, better SCE, and small parasitic capacitance simultaneously. In this work, a leading-edge 90nm CMOSFET technology was used as a vehicle to demonstrate device performances. For conventional device with vertical gate, an additional 10nm offset spacer module was implemented. Results and Discussions The schematic view and cross section SEM for the notch-gate devices with tensile stress CESL are shown in Fig. 1 and 2, respectively. Fig. 3 shows the simulated CESL stress distribution, which found that the notch-gate device possesses higher induced tensile channel stress than the vertical-gate device does. Extra 7% driving capability of nMOSFET for an off current 10nA/um at 1V can be obtained, as shown in Fig. 4. We believe that the increase in ID is due to the CESL-induced tensile stress in the channel region more directly especially for device’s gate was notch. Fig. 5 shows a simulated halo profile for both nMOSFETs at 90nm gate length with the same threshold voltage. It was found that a notch-gate device own very localized indium halo profile, and thus possesses better Vth roll-off and DIBL characteristics than vertical-gate device does, as shown in Fig. 6. However for notch-gate device, more oxide defects were generated due to notch-gate process and higher tensile stress in the channel region, resulting in slightly higher gate leakage, as shown in Fig. 7. Oxide and interface defects can be identified using a low frequency noise measurement, as described in Fig. 8. It was found that notch-gate device has slightly higher oxide defects and equal Si/oxide interface defects Dit. However, the driving capability of notch-gate nMOSFET has not been degraded apparently by these oxide defects. A charge pumping current monitor revealed less Dit occurring in the notch-gate nMOSFET with a small effective poly overlap active area. Compared with vertical-gate nMOSFET with an additional offset spacer, device with a notch-gate as self-aligned offset spacer possess less gate to S/D overlap as well as more localized halo profile, thus exhibiting lower overlap S/D capacitances CGD (Fig. 9) and effective junction capacitance Cj (Fig. 10) in respectively. Similar to nMOSFET with simulated data supporting, notch-gate pMOSFET shows more localized Arsenic halo profile in comparison with vertical-gate pMOSFET does, thus possesses better Vth roll-off and DIBL characteristics (Fig. 11) as well as exhibits better device’s driving capability, as shown in Fig.12. However, the increase of driving capability of pMOSFET (3%) is less than that of nMOSFET (7%) because the tensile CESL-induce stress is inappropriate for pMOSFET [4]. For pMOSFET, a compressive stress is more effective method to improve channel mobility. However, even with inappropriate effect by tensile CESL stress, the driving capability of pMOSFET still can be enhanced with an optimal channel profile by halo implanted through the notch-gate structure. Fig. 13 reveals that higher gate leakage was found in notch-gate device, which can be proved by low frequency noise measurement (Fig. 14). Compared to vertical pMOSFET, lower Cj and CGD can be found at notch-gate device with a self-aligned offset spacer and localized halo profile, as shown in Fig. 15 and 16, respectively. In this work, for 90nm notch-gate CMOSFET with high stress CESL, good device performance with saturated drain currents of 1160 uA/um (nFET) and 460uA/um (pFET) for an off current 100nA/um at 1V can be obtained, as shown in Table I. Conclusions This paper shows a highly manufacturable method to improve the driving capability for sub-90nm CMOSFET without introducing specific additional processes. Based on simulation and measurement, we have shown that combining a notch-gate structure with high tensile stress CESL can efficient enhance channel mobility, better SCE, lower CGD and Cj simultaneously. For nMOSFET, efficient CESL-induced stress can be enhanced though notch-gate edge into channel center is major reason to improve device’s driving capability. For pMOSFET, even with inappropriate tensile stress, notch-gate pMOSFET with optimal channel profile shows better performance than vertical-gate device does. Therefore, integrating notch-gate structure with a stressed-CESL is a quite efficient and simple method to optimize CMOSFET performance. This work was supported by National Science Council under Contracts NSC95-2221-E-390-028. [1] C.-H. Ge, et. al, in IEDM Tech. Dig., 2003, p. 73. [2] G. Eneman, et. al, in VLSI Tech. Dig., 2005, p. 22. [3] T. Ghani, et. al, in IEDM Tech. Dig., 1999, p. 415. [4] D. Wu, et. al, in Proc. SSIC Tech. Dig., 2001, p. 539. [5] S. Pidin, et. al, in Symp. VLSI Tech. Dig., 2001, p. 35. [6] T. Komoda, et. al, in IEDM Tech. Dig., 2004, p. 217. Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, Tsukuba, 2007, -410P-3-3 pp. 410-411