Yaorong Su

Self-Assembled Monolayers of Phosphonic Acids with Enhanced Surface Energy for High-Performance Solution-Processed N-Channel Organic Thin-Film Transistors†

A self-assembled monolayer (SAM) is only a few nanometers thick, but can dramatically change the surface properties. Herein we report novel SAMs of phosphonic acids (shown in Figure 1a), which are completely wettable by various organic solvents because of the enhanced surface energy of the SAMs, leading to solution-processed n-channel organic thin-film transistors (OTFTs) with average field effect mobility as high as 1.6 cmV 1 s . OTFTs are elemental units in organic integrated circuits that, for example, operate radio-frequency identification (RFID) tags and sensors and are used to drive individual pixels in active matrix displays. For these applications, solution-processed OTFTs can be fabricated onto flexible substrates over a large area at low cost using rollto-roll or ink-jet printing techniques. OTFTs are interface devices with their performance highly dependent on the interface between organic semiconductors and gate dielectrics no matter whether the organic semiconductors are processed by vacuum deposition or solution-based methods. Owing to the key importance of the semiconductor–dielectric interface, great efforts have been made in interface engineering to control the interface structures, such as molecular ordering, surface dipoles, and film morphology. By virtue of their ability to manipulating the surface properties, SAMs of organosilanes and phosphonic acids have been developed as a very powerful tool to modify the dielectric oxide surface in OTFTs, particularly vacuum-deposited OTFTs. It is worth noting that the success of a specific SAM in vacuumdeposited OTFTs is often barely duplicated in solutionprocessed OTFTs, and controlling the morphology of solution-processed films of organic semiconductors is usually complex. One key factor that affects the nucleation and

Self‐Assembled Monolayers of Cyclohexyl‐Terminated Phosphonic Acids as a General Dielectric Surface for High‐Performance Organic Thin‐Film Transistors

A novel self-assembled monolayer (SAM) on AlOy /TiOx is terminated with cyclohexyl groups, an unprecedented terminal group for all kinds of SAMs. The SAM-modified AlOy /TiOx functions as a general dielectric, enabling organic thin-film transistors with a field-effect mobility higher than 5 cm(2) V(-1) s(-1) for both holes and electrons, good air stability with low operating voltage, and general applicability to solution-processed and vacuum-deposited n-type and p-type organic semiconductors.

Low-Voltage Organic Field-Effect Transistors (OFETs) with Solution-Processed Metal-Oxide as Gate Dielectric

In this study, low-voltage copper phthalocyanine (CuPc)-based organic field-effect transistors (OFETs) are demonstrated utilizing solution-processed bilayer high-k metal-oxide (Al(2)O(y)/TiO(x)) as gate dielectric. The high-k metal-oxide bilayer is fabricated at low temperatures (< 200 °C) by a simple spin-coating technology and can be controlled as thin as 45 nm. The bilayer system exhibits a low leakage current density of less than 10(-5) A/cm(2) under bias voltage of 2 V, a very smooth surface with RMS of about 0.22 nm and an equivalent k value of 13.3. The obtained low-voltage CuPc based OFETs show high electric performance with high hole mobility of 0.06 cm(2)/(V s), threshold voltage of -0.5 V, on/off ration of 2 × 10(3) and a very small subthreshold slope of 160 mV/dec when operated at -1.5 V. Our study demonstrates a simple and robust approach that could be used to achieve low-voltage operation with solution-processed technique.

A low-temperature, solution-processed high-k dielectric for low-voltage, high-performance organic field-effect transistors (OFETs)

We report here a low-temperature, solution-processed high-k dielectric, which can be used effectively to achieve high-performance, low-voltage organic field-effect transistors (OFETs). A CuPc device based on the solution-processed dielectric possessed a mobility of 0.15cm 2 V ! 1 s ! 1 under a voltage of only ! 2V, which is more than one order of magnitude higher than that obtained on traditional 300nm SiO2 under ! 40V. Detailed studies by atomic force microscopy and grazing incidence x- ray diffraction reveal that the high performance can be attributed to the crystallized interconnected rod-like structure of CuPc molecules in the initial growth on ATO. Pentacene and rubrene single crystal FETs on the solution-processed dielectric also exhibit higher performance than those on 300nm SiO2. Our findings suggest that the low-temperature, solution-processed high-k dielectric can be a plausible choice for fabrication of high-performance low-voltage OFETS, and also provide some clues in designing effective high-k dielectrics.

Insights into the interfacial properties of low-voltage CuPc field-effect transistor.

The interfacial transport properties and density of states (DOS) of CuPc near the dielectric surface in an operating organic field-effect transistor (OFET) are investigated using Kelvin probe force microscopy. We find that the carrier mobility of CuPc on high-k Al2Oy/TiOx (ATO) dielectrics under a channel electrical field of 4.3 × 10(2) V/cm reaches 20 times as large as that of CuPc on SiO2. The DOS of the highest occupied molecular orbital (HOMO) of CuPc on the ATO substrate has a Gaussian width of 0.33 ± 0.02 eV, and the traps DOS in the gap of CuPc on the ATO substrate is as small as 7 × 10(17) cm(-3). A gap state near the HOMO edge is observed and assigned to the doping level of oxygen. The measured HOMO DOS of CuPc on SiO2 decreases abruptly near E(V(GS) = V(T)), and the pinning of DOS is observed, suggesting a higher trap DOS of 10(19)-10(20) cm(-3) at the interface. The relationships between DOS and the structural, chemical, as well as electrical properties at the interface are discussed. The superior performance of CuPc/ATO OFET is attributed to the low trap DOS and doping effect.

Low-voltage flexible pentacene thin film transistors with a solution-processed dielectric and modified copper source–drain electrodes

Low-voltage, flexibility and low-cost are essential prerequisites for large scale application of organic thin film transistors (OTFTs) in future low-end electronics. Here, we demonstrate a low-voltage flexible OTFT by using a low-temperature, solution-processed gate dielectric. Such a dielectric can be well integrated with an Au coated polyimide film, and exhibits a low leakage current density of less than 10−6 A cm−2 and a high capacitance density of 180 nF cm−2. Pentacene films deposited onto the solution-processed dielectric show a highly ordered “thin film phase”. The source–drain (S/D) electrodes are made of in situ modified Cu encapsulated by Au (Au/M-Cu). The obtained flexible OTFT exhibits outstanding electrical characteristics under a gate voltage of only −2 V, which include an on/off ratio of 2 × 104, a mobility (μ) of 1.5 cm2 V−1 s−1, a threshold voltage (VT) of −0.3 V and a subthreshold slope (SS) of 161 mV dec−1. The obtained mobility value is among the highest achieved in flexible pentacene OTFTs. The mechanical flexibility and reliability of the OTFTs are also studied and discussed in detail, and the observed degradation of the device performance under strains is attributed to the damage induced in the electrodes giving rise to increased contact resistance and the phase transition from the thin film phase to bulk phase of the pentacene films.

Low-voltage graphene field-effect transistors based on octadecylphosphonic acid modified solution-processed high-k dielectrics

In this study, a solution-processed bilayer high-k dielectric (Al2O(y)/TiO(x), abbrev. as ATO) was used to realize the low-voltage operation of graphene field-effect transistors (GFETs), in which the graphene was grown by atmospheric pressure chemical vapor deposition (APCVD). Upon modifying the interface between graphene and the dielectric by octadecylphosphonic acid (ODPA), outstanding room-temperature hole mobility up to 5805 cm(2) V(-1) s(-1) and electron mobility of 3232 cm(2) V(-1) s(-1) were obtained in a small gate voltage range from -3.0 V to 3.0 V under a vacuum. Meanwhile, an excellent on/off current ratio of about 8 was achieved. Our studies demonstrate an effective route in which utilizing the low-temperature solution-processed dielectrics can achieve low-voltage and high performance GFETs.