Yasir Hashim

Temperature effect on I-V characteristics of Si nanowire transistor

This paper represents the temperature effect on silicon nanowire transistor and the possibility of using it as a temperature nanosensor. MuGFET simulation tool was used to investigate temperature characteristics of the nanowire transistors. Current-voltage characteristics with different values of temperature were simulated. Variation of sub threshold slope (SS), ON current to OFF current ratio (Ion/Ioff) and drain induced barrier lowering (DBIL) with working temperature was investigated. MOS diode connection suggested using the silicon nanowire transistor as a temperature nanosensor.

Temperature effect on ON/OFF current ratio of FinFET transistor

This paper demonstrates the working temperature effect on ON/OFF current ratio of FinFET transistor and the prospect of using it as a temperature nano-sensor. The characteristics of the FinFET transistors were simulated using MUGFET simulation tool at different working temperature. Output characteristics with a working temperature range (−25°C to 125°C) were simulated. Variation of ON current to OFF current ratio (Ion/Ioff) with working temperature was investigated.

Characterization of silicon nanowire transistor as a temperature nano-sensor device

This paper represents the temperature characteristics of silicon nanowire transistor of rectangular cross-section, temperature effect on transfer characteristics, ION/1oFF ratio and sub-threshuld swing was studied. OMEN nanowire simulation tool was used to investigate temperature characteristics of transistor with three types of orientations. The findings of the current study reveal that <;111> and <;100> are the best types of orientations to be used in SiNWT for the temperature application of electronic circuits, such as digital circuits and amplifiers, because of the high ION/1oFF ratio and lower SS at these orientations. Moreover, the best orientation for temperature sensor was <;110> because of the larger carrier velocity and smaller channel resistance.

Dimensional Effect on DIBL in Silicon Nanowire Transistors

Drain-induced barrier lowering (DIBL) is crucial in many applications of silicon nanowire transistors. This paper determined the effect of the dimensions of nanowires on DIBL. The MuGFET simulation tool was used to investigate the characteristics of the transistors. The transfer characteristics of transistors with different dimensions were simulated. The results show that longer nanowires with smaller diameters and lower oxide thickness decrease DIBL and tend to possess the best transistor characteristics.

Nano-Dimensional Properties of Si-FinFET Transistor Based on I ON /I OFF Ratio and Subthreshold Swing (SS)

This paper presents design the optimal channel dimensions for Silicon Fin Feld Effect Transistor (Si-FinFET) for improvement electrical characteristic of Si-FinFET depending on the electrical characteristics of the channel (I ON /I OFF , SS, VT, DIBL). The MuGFET simulation tool has been using to investigate the electrical characteristics of Si-FinFET. The current voltage characteristics has been simulating with different dimensions channel (length, width and oxide thickness). The best channel dimensions of Si-FinFET observed based on electrical characteristics at the working voltage VDD range of 0-5 V. Note that the results with the scaling channel dimensions. Depending on I ON /I OFF ratio higher value, and nearest SS to the ideal SS, the best scaling channel dimensions (K) will be K=0.25 at VDD=5 V and K=0.25 at VDD=0.5 V.

Optimization of Resistance Load in 4T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor

This study explores optimization of resistance load (R-Load) of four silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. Noise margins and inflection voltage of butterfly characteristics with static power consumption of SRAM cell are used as limiting factors in this optimization. Range of R-Load used in this study was 20-1000 KΩ with Vdd = 1 V. Results indicate that optimization depends critically on resistance load value. The optimized range of R-Load is 100-200 KΩ.

A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor

This study explores dimensional optimization at different high logic-level voltages for six silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. This study is the first to demonstrate diameter and length of nanowires with different logic voltage level (V dd optimizations of nanoscale SiNWT-based SRAM cell. Noise margins and inflection voltage of butterfly characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on nanowire dimensions and V dd. The increase in V dd from 1 V to 3 V tends to decrease the dimensions of the optimized nanowires but increases the current and power. SRAM using nanowire transistors must use V dd of 2 or 2.5 V to produce SRAM with lower dimensions, inflection currents, and power consumption.

Optimization of channel length nano-scale SiNWT based SRAM cell

This paper represents a channel length ratio optimization at a different high logic level voltage for 6-Silicon Nanowire Transistors (SiNWT) SRAM cell. This study is the first to demonstrate an optimized length ratio of nanowires with different Vdd of nano-scale SiNWT based SRAM cell. Noise margins (NM) and inflection voltage (Vinf) of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both length ratios of nanowires and logic voltage level (Vdd), and increasing of high logic voltage level of the SiNWT based SRAM cell tends to decrease in the optimized nanowires length ratio with decreasing in current and power.

A new simulation model for nanowire-CMOS inverter circuit

This This paper is to suggest a new model for predicting the static characteristics of nanowire-CMOS (NW-CMOS) inverter. This model depends on experimental (or simulated) output characteristics of load and driver transistors separately as an input data. This model used in this research to investigate the effect of length (L), oxide thickness (Tox) and numbers of nanowires in P and N-channel SiNWT on the NW-CMOS inverter output and current characteristics. This study used MuGFET simulation tool to produce the output characteristics of SiNWT which used as input to a designed MATLAB software to calculate the characteristics of NW-CMOS. The output (Vout-Vin) and current (Iout-Vin) characteristics that calculated shows excellent behaviors for digital applications.

Diameter optimization of Nano-scale SiNWT based SRAM cell

This paper represents diameter and logic voltage level optimizations of 6-Silicon Nanowire Transistors (SiNWT) SRAM. This study is to demonstrate diameter of nanowires effects at a different logic voltage level (Vdd) on the static characteristics of Nano-scale SiNWT Based SRAM Cell. Noise margins (NM) and inflection voltage (Vinf) of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both diameters of nanowires and logic voltage level (Vdd). And increasing of logic voltage level from 1V to 3V tends to decrease in optimized nanowires diameters but with increasing in current and power dissipation. SRAM using nanowires transistors must use logic level (2V or 2.5V) to produce SRAM with lower diameters and suitable inflection currents and then with lower power dissipation as possible.