Yasser Mohanna

Teaching microprocessors, microcontrollers, and digital signal processing courses using only one target processor: The newborn dsPIC30F™ from Microchip™

As the technology of electrical and computer engineering (E&CE) grows, undergraduate programs are under constant pressure to keep content up‐to‐date within a 4‐year context of a fixed number of credits hours allowed for graduation. Teaching Microprocessors, Microcontrollers and Digital Signal Processing using only one target processor (dsPIC30F™) can save many credit hours and efforts. The newborn dsPIC30F from Microchip is a microcontroller with digital signal processing power and a new Harvard architecture. In addition, the same processor can be easily used in lab experiments, final year projects and research works.

Dynamic and Partial Reconfiguration Power Consumption Runtime Measurements Analysis for ZYNQ SoC Devices

Field Programmable Gate Array (FPGA) architectures, such as Xilinxs Virtex-4 up to 7 series, have enabled partial and dynamic run-time self-reconfiguration for a long time. This feature enables the substitution of parts of a hardware design implemented on this re-configurable hardware, and therefore makes it possible for a system to adapt to the actual demands of applications. Dynamic Partial Reconfiguration (DPR) is an interesting technique that permits to share a part of the FPGA between different dedicated functions or hardware accelerators. Many domains may benefit from this technique including the Internet of Things (IoT), automotive industry, etc. However, many parameters, such as reconfiguration overhead, idle power consumption and performance trade-off, must be considered. In this paper, we provide a precise estimation of the power consumption when the DPR process is running in order to evaluate its influence on the performance of the global design. For this purpose, a Software/Hardware (SW/HW) system was implemented and the results were extracted in real-time using Zynq System on Chip SoC devices.

NISC-Based Soft-Input–Soft-Output Demapper

Applications in wireless digital communication field are becoming increasingly complex and diverse. Circuits and systems adopted in this application domain must not only consider performance and implementation constraints but also the requirement of flexibility. The combination of flexibility and the ever increasing performance requirements demands design approach that provides better ways of controlling and managing hardware resources. An application-specific instruction-set processor (ASIP) design approach is a key trend in designing flexible architectures. The ASIP concept implies dynamic scheduling of a set of instructions that generally leads to an overhead related to instruction decoding. The no-instruction-set-computer (NISC) concept has been introduced to reduce this overhead through the adoption of static scheduling. In this brief, the NISC approach is explored through a case-study design of universal demapper for multiple wireless standards. The proposed design has common main architectural choices as a state-of-the-art ASIP for comparison purpose. The obtained results illustrate a significant improvement in execution time and implementation area while using identical computational resources and supporting same flexibility parameters.

ARM-FPGA based platform for automated adaptive wireless communication systems using partial reconfiguration technique

Recent fixed and mobile wireless communication systems have attracted researchers to propose new techniques and methodologies that greatly improve performance. For example, adaptive techniques have improved the wireless channel efficiency while decreasing the overall power consumption. They consist in reconfiguring parts of the global system automatically according to different parameters. In parallel, circuit technology has also considerably evolved. One example is Field Programmable Gate Arrays (FPGAs) that are now suitable for implementing the physical layer of most complex wireless communication systems. This has been made possible thanks to their high level of performance, flexibility, and bit-level programming. In these devices, the Dynamic Partial Reconfiguration (DPR) constitutes a well known technique for reconfiguring only a specific area within the circuit. This technique offers efficient resource utilization, reduced power consumption and permits the optimization of the configuration time. In our work, we benefit from this technology to implement a wireless communication system in hardware. Hardware reconfiguration is performed automatically according to adaptive decision processes running on top of a micro-kernel that manages partial reconfiguration. The system is implemented on a ZedBoard which features a Xilinx Zynq 7000 System on Chip (SoC).

Newton-Raphson Solution of Poisson's Equation in a Pn Diode:

This paper presents a numerical solution, using MATLAB, of the electrostatic potential in a pn junction, which obeys Poissons equation. This numerical method is based on the Newton-Raphson technique and is useful for educational purposes. It can be incorporated in an undergraduate course on semiconductor devices to demonstrate the applications of numerical analysis techniques in device physics. It may also be appropriate for a section on numerical analysis techniques in an engineering mathematics course.

Study of the effects of signal filtering on acousto-optic correlator performance

The performance of acousto-optic correlators (AOC) in spread-spectrum receivers is considered. The received pseudorandom sequences are correlated with reference ones in an acousto-optic cell. In particular, the effects of receiver filtering on the AOC processing gain are analyzed in the presence of additive white Gaussian noise (AWGN). The signal processing method is presented. For ideal AOCs, simple analytical expressions are derived for two different types of receiver filters: ideal and RC first-order filters. The results are given in terms of the ratio β of the code rate to the filter bandwidth. They show approximate processing gain losses of 4 dB for the first type and 1 dB for the second type for β=5. For real AOCs, the results are obtained from numerical simulation.

Design and prototyping flow of NISC-based flexible MIMO turbo-equalizer

Flexible design implementations are increasingly explored in digital communication applications to cope with diverse configurations imposed by the emerging communication standards. On the other hand, rapid hardware prototyping is a crucial requirement in system validation and performance evaluation under various use case scenarios. Adding flexibility, and hence increasing system complexity on one hand, and shrinking design time to meet with market pressure on the other hand, require a productive design approach ensuring final design quality. By eliminating the instruction set overhead, No- Instruction-Set-Computer (NISC) approach fulfills these design requirements offering static scheduling of datapath, automated RTL synthesis and allowing designer to have direct control of hardware resources. This paper presents a case study of an NISC-based implementation of a flexible low-complexity MIMO turboequalizer. The complete design and prototype flow, from architecture specification till FPGA implementation, is described in details. Using VC707 evaluation board integrating Xilinx Virtex-7 FPGA, the prototype of 2×2/4×4 spatially multiplexed MIMO system achieves a throughput of 115.8/62.4 Mega symbols per second at a clock cycle frequency of 202.67 MHz. Furthermore, the flexibility of the demonstrated prototype allows to support all communication modes defined in LTE, WiFi, WiMAX, and DVB-RCS wireless communication standards.

Quantization and fixed-point arithmetic for MIMO MMSE-IC linear turbo-equalization

In digital communication applications, floating-point arithmetic is generally used to conduct performance evaluation studies of new proposed algorithms. This is typically limited to theoretical performance evaluation in terms of communication quality and error rates. For a practical implementation perspective, using fixed-point arithmetic instead of floating-point reduces significantly the costs in terms of area occupation and energy consumption. However, this implies a complex conversion process, particularly if the considered algorithm includes complex arithmetic operations with high accuracy requirements and if the target system presents many configuration parameters. In this context, the purpose of the paper is to investigate the influence on error rate performance related to the implementation of minimum mean-squared error (MMSE) linear turbo-equalization algorithm for multiple-input multiple-output (MIMO) systems utilizing fixed-point rather than floating-point arithmetic.

A new approach to 3D form recognition within video capsule endoscopic

This paper describes a novel approach to capsular endoscopy that takes advantage of existing wireless capsule endoscopy (WCE) and overcomes some of its important limits. The basic and essential task concerning the integration of SVM classifier is listed and discussed in details, as well as the new features required to improve its diagnostic capability. In addition, a large scale demonstrator has been evaluated and tested. In vitro experimental results were encouraging and show correct classification rate of intestinal polyps of approximately 93.7%. The work contains detailed statistics about the detection rate and the computing complexity.

Demo: WIFI-WiMax vertical handover on an ARM-FPGA platform with partial reconfiguration

In recent wireless networks, end-nodes are capable of detecting the existence of multiple wireless standards. In this context, it becomes very interesting to design an on-line reconfigurable communication system controlled by a Vertical Handover Algorithm (VHA) that allows selecting the best available wireless standard. In this demo, we propose implementing the Partial Reconfiguration (PR) technique on a platform based on ARM-FPGA SoC device to apply vertical handover between two wireless communication standards; WIFI and Wimax. The demo simulates the mobility of an end-node in an WIFI-WiMax network on a GUI Interface connected to a ZedBoard. On the board, the VHA senses specific parameters and decides accordingly to reconfigure a unified chain before applying partial reconfiguration on the device.