Yasuaki Hagiwara | Researchain

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Publication

Featured researches published by Yasuaki Hagiwara.

Archive | 2003

High-performance, superscalar-based computer system with out-of-order instruction execution

Le Trong Nguyen; Derek J. Lentz; Yoshiyuki Miyayama; Sanjiv Garg; Yasuaki Hagiwara; Johannes Wang; Te-Li Lau; Sze-Shun Wang; Quang H. Trang

Archive | 2006

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

Le Trong Nguyen; Derek J. Lentz; Yoshiyuki Miyayama; Sanjiv Garg; Yasuaki Hagiwara; Johannes Wang; Te-Li Lau; Sze-Shun Wang; Quang H. Trang

Archive | 1992

Microprocessor architecture capable of supporting multiple heterogeneous processors

Derek J. Lentz; Yasuaki Hagiwara; Te-Li Lau; Cheng-Long Tang; Le Trong Nguyen

Archive | 1991

Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

Derek J. Lentz; Yasuaki Hagiwara; Te-Li Lau; Cheng-Long Tang; Le Trong Nguyen

Archive | 1992

RISC microprocessor architecture implementing fast trap and exception state

Le Trong Nguyen; Derek J. Lentz; Yoshiyuki Miyayama; Sanjiv Garg; Yasuaki Hagiwara; Johannes Wang; Quang H. Trang

Archive | 1995

Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption

Derek J. Lentz; Yasuaki Hagiwara; Te-Li Lau; Cheng-Long Tang; Le Trong Nguyen

Archive | 1995

System and method for processing multiple requests and out of order returns

Le Trong Nguyen; Yasuaki Hagiwara

Archive | 1999

System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit

Derek J. Lentz; Yasuaki Hagiwara; Te-Li Lau; Cheng-Long Tang; Le Trong Nguyen

Archive | 1997

Microprocessor architecture with a switch network and an arbitration unit for controlling access to memory ports

Derek J. Lentz; Yasuaki Hagiwara; Te-Li Lau; Cheng-Long Tang; Le Trong Nguyen

Archive | 1992

Extensible risc microprocessor architecture

Sanjiv Garg; Yasuaki Hagiwara; Tei-Li Lau; Derek J. Lentz; Yoshiyuki Miyayama; Le Trong Nguyen; Quang H. Trang; Johannes Wang

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