Yasunari Mori

Large Scaled ALD/PECVD Reactor for Flat Panel Display Application

Rapid progress of a light-weight and highresolution in a compact size Liquid Crystal Display presses on a research of a high performance of a LowTemperature-Poly-Silicon (LTPS) TFT. High quality gate insulator is a one of the key technologies to enhance its performance. General method to prepare the gate insulator of TFT is a parallel plate type Plasma Enhanced Chemical Vapor Deposition (PECVD) method, using Tetraethylorthosilicate (TEOS) as the source gas. However, the prepared SiO2 films have many defects caused by plasma damage in them. Decrease of their defects is requested for high-performance LTPS-TFT. Recently, an Atomic Layer Deposition (ALD) technology has attracted much attention as a new technology in LSI s. The ALD film has attractive features of precise thickness control and high conformity, because of the alternating gas supply. However, growth rate of the ALD film is not satisfactory for preparing the 50-100nmthick gate insulator of the TFT. We have developed a low energy monopole antenna plasma technology. The plasma is very high frequency (VHF) electromagnetic wave coupled type. It is expected that the plasma does not give severe damage to the film surface, because it is localized around the monopole antenna, and its electron temperature at the substrate position is low. We propose an all-new stacked gate insulator, which is prepared with the ALD technology for an interfacial layer, and the monopole antenna PECVD technology for a secondary layer (1). We developed the ALD/PECVD reactor, which handles glass substrates of 370mm×470mm in size (2). Figure 1 shows appearance of the reactor. Deposition of the ALD-SiO2 is conducted at the temperature of 200400 with alternating exposures of Aminosilane and oxidizer; ozone or radical oxygen by plasma. Secondary layer is deposited on the ALD film by the monopole antenna PECVD method. TEOS and O2 gas were used for material source of the PECVD method. The substrate temperature, power and frequency were 200-400 , 1000W-4500W and 80MHz, respectively. Metal-oxide-semiconductor (MOS) capacitors were prepared to evaluate electrical properties of the films. The film was deposited on p-type Si wafers (100), which were set on 370mm×470mm glass substrate. As a gate electrode, aluminum was deposited on the films. Postannealing process was conducted in a forming gas (H2 10% + N2 90%) atmosphere at 400 for 30 minutes. Thicknesses of the films were evaluated with an ellipsometer. Figure 2 shows thickness distribution of the ALD-SiO2 film on the 370mm×470mm glass. Thicknesses variation on the glass were less than 5%. Typical deposition rates were 0.1nm/cycle, and varied by gas exposure conditions. Surface of the 20nm-thick ALDSiO2 film was very smooth, and its Ra was 0.1nm in 1 m. Conformal film growth was observed with patterned substrates. The ALD/PECVD stacked film was deposited with 2nm-ALD film followed by 100nm-PECVD deposition. Typical deposition rate and the thickness variation of the PECVD were 50nm/min and 10%, respectively. Figure 3 shows C-V performance of the stacked SiO2 film deposited at 400 . The stacked film has excellent electrical properties of an interface trap density of 1×10cmeV, and an electrical field of 7.5MVcm at a leakage current of 1×10Acm. It is expected that high performance LTPS-TFT is obtained with this stacked insulator.