Yasushi Akasaka

Oxygen Vacancy Induced Substantial Threshold Voltage Shifts in the Hf-based High-K MISFET with p+poly-Si Gates -A Theoretical Approach

A theoretical investigation has been made of the origin of substantial threshold voltage (Vth) shifts observed in p+poly-Si gate Hf-based metal insulator semiconductor field effect transistors (MISFETs), by focusing on the effect of oxygen vacancy (VO) formation in HfO2. It has been found that VO formation and subsequent electron transfer across the interface definitely causes substantial Vth shifts, especially in p+poly-Si gate MISFETs. Moreover, the theory also systematically reproduces recent experimental reports that large flat band (Vfb) shifts are observed, even in intrinsic poly-Si gates, and that the Vfb shifts exhibit a high dependence on HfSiOx thickness.

Modified Oxygen Vacancy Induced Fermi Level Pinning Model Extendable to P-Metal Pinning

Typical p-metals show similar effective work functions close to p+ polycrystalline silicon (poly-Si) pinning position irrespective of materials after high-temperature process. We found that this phenomenon can be explained by the modified Vo model taking into account the effect of Si substrate. Oxygen absorption by Si substrate and subsequent electron transfer to metal electrode clearly explain the p-metal Fermi level pinning as well as p+ poly-Si pinning. In addition, unsuppressed Fermi level pinning by insertion of barrier layer at p+ poly-Si/barrier layer/high-k gate stack, which is one of the open issues concerning p+ poly-Si pinning, has the same overall reaction scheme. The modified model also consistently explains this phenomenon.

Low-resistivity poly-metal gate electrode durable for high-temperature processing

A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100 nm)WN/sub x/(5 nm)/poly-Si structure. The W/WSiN/poly-Si structure was found to be thermally stable even after annealing at 800/spl deg/C. The sheet resistivity of the W(100 nm)/WN/sub x/(5 nm)/poly-Si(100 nm) structure is as low as 1.5 /spl Omega//spl par//spl square/ and independent of line-width from 0.52 /spl mu/m to 0.12 /spl mu/m. The sheet resistivity of this layer structure is 40% lower than that of the W(100 nm)/TiN(5 nm)/poly-Si structure. In addition, an equivalent circuit simulation showed that the measured contact resistivity of W and poly-Si in the W/WSiN/poly-Si system did not affect the gate RC delay time. Finally, a process integration of the poly-metal gate electrode is discussed. A SiN capped poly-metal structure was demonstrated.

High performance damascene metal gate MOSFETs for 0.1 /spl mu/m regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (/spl sim/1000/spl deg/C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450/spl deg/C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance.

Physics in Fermi level pinning at the polySi/Hf-based high-k oxide interface

We report that O vacancy (Vo) formation in ionic Hf-based dielectrics and subsequent electron transfer into poly Si gates across the interface, definitely cause substantial flat band (Vfb) shifts especially for p+ gate MISFETs. Our theory can systematically reproduce experiments related to Hf-based dielectrics, and gives a guiding principle towards gate/high-k oxide interface control.

Tenth micron p-MOSFET's with ultra-thin epitaxial channel layer grown by ultra-high-vacuum CVD

We have, for the first time, demonstrated silicon MOSFETs with an ultra-thin epitaxial channel grown by low-temperature UHV-CVD; this allows the channel region to be doped with high precision. The boron concentration and epitaxial layer thickness can be chosen independently, so it is easily possible to adjust the threshold voltage of the p-MOSFETs even in the case of n-type polysilicon gates. It was confirmed that choosing an ultra-thin epitaxial layer-in the 10 nm range-leads to suppression of the short-channel effects in n-type polysilicon gate buried-channel MOSFETs, while maintaining an appropriate value of threshold voltage.<<ETX>>

Formation mechanism of ultrathin WSiN barrier layer in a W/WNx/Si system

Abstract A W/WN x /poly-Si composite structure (poly-metal) has been proposed as a low resistivity gate material. It has been found that an ultrathin WSiN layer forms at the W/Si interface after annealing, and as a result, the W/WSiN/poly-Si structure is very stable up to 950°C. In this paper, the formation mechanism of the ultrathin WSiN layer was studied. It was found that a 1 nm WSiN layer forms by solid state reaction between the WN x and poly-Si during annealing. A part of nitrogen atoms originally incorporated in the WN x film react with Si to form a 1 nm WSiN layer during annealing. Chemical bonds in the ultrathin WSiN layer consists of SiN bonds and metallic W bonds. Metallic W bonds are attributed to WW or WSi bonds. There is no WN bonds. Therefore, it is speculated that the WSiN consists of Si 3 N 4 and W or WSi x , and stabilizes the W/poly-Si interface. Since the WSiN layer acts as an excellent barrier metal for W and Si diffusion, the sheet resistivity of the poly-metal structure (where W thickness is 100 nm) can be maintained to be lower than 1.5 ω/sq.

P-MOSFET's with ultra-shallow solid-phase-diffused drain structure produced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1- mu m and sub-0.1- mu m devices. Highly doped ultrashallow p/sup +/ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p/sup +/-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved. >

Characterization of HfSiON gate dielectrics using monoenergetic positron beams

The impact of nitridation on open volumes in thin HfSiOx films fabricated on Si substrates by atomic layer deposition was studied using monoenergetic positron beams. For HfSiOx, positrons were found to annihilate from the trapped state due to open volumes which exist intrinsically in an amorphous structure. After plasma nitridation, the size of open volumes decreased at a nitrogen concentration of about 20at.%. An expansion of open volumes, however, was observed after postnitridation annealing (PNA) (1050°C, 5s). We found that the size of open volumes increased with increasing nitrogen concentration in HfSiOx. The change in the size of open volumes was attributed to the trapping of nitrogen by open volumes, and an incorporation of nitrogen into the amorphous matrix of HfSiOx during PNA. We also examined the role of nitrogen in HfSiOx using x-ray photoelectron spectroscopy and first principles calculations.

W/WNx/poly-Si gate technology for future high speed deep submicron CMOS LSIs

In this paper, a new gate structure, W/WNx/poly-Si, was proposed as the breakthrough to combat the serious parasitic effect caused by RC delay of gate electrode in down-scaled CMOS devices. MOSFETs with the gate electrode structure were fabricated with a deep submicron CMOS process. As a result, 1.6/spl Omega//spl square/ gate sheet resistance without an increase in fine line gate was obtained. Moreover, it was demonstrated that the thin WNx layer formed by reactive sputtering can be an excellent barrier layer from the gate oxide integrity and W/poly-Si contact resistivity point of view.<<ETX>>