Yasushi Kanoh

A DSM architecture for a parallel computer Cenju-4

A parallel computer Cenju-4 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor and designed to be scalable up to 1024 nodes. For scalability, Cenju-4 adopts a bit-pattern directory. This scheme enables more precise representation than other imprecise schemes, such as a coarse vector scheme. Cenju-4 utilizes multicast and gathering functions of the network for delivering invalidation request messages and for collecting replies. This enables store access latency to be scalable, even when the block is shared among all nodes. Cenju-4 also prevents starvation and deadlock by queuing certain types of messages in the main memory. This enables a full solution to the starvation problem with centralized directory scheme, and to the deadlock problem with one physical or virtual network. The buffer sizes required for queuing messages at each node are only 32K bytes and two 64K bytes on a 2024-node system. In this paper, we present the design of the DSM architecture and some performance results.

Message Passing Communication in a Parallel Computer Cenju-4

Cenju-4 is a parallel computer designed and manufactured by NEC Corp. Cenju-4 supports two memory architectures: distributed memory with user-level message passing communication and distributed shared memory with cache-coherent non-uniform memory access (cc-NUMA) feature. The Cenju-4 system consists of from 8 to 1024 nodes connected by a multistage network which has multicast, synchronization, and gather functions. Each node has a MIPS R10000 processor with up to 512 Mbyte main memory. This paper describes the architecture of Cenju-4, especially its multistage network and network interface. In addition, performance results are presented for message passing communication.

Architecture of a parallel machine : Cenju-3

Cenju-3 is a parallel computer in which up to 256 processing elements (PEs) are connected by a highspeed multistage interconnection network. In designing the system, the architecture is tuned for up to a 256 processor system. A VR4400 with 1 MB of secondary cache memory is implemented on a multi-chip-module to realize a compact and high-performance PE. The multistage network is implemented very compactly. The number of the cables is equal to the number of processors. The dedicated network interface hardware designed for the system achieves low latency and high throughput. This paper presents the machine architecture and its evaluation.

Architecture of a parallel computer Cenju-4

This paper describes the architecture and the evaluation results of a parallel computer Cenju-4. Cenju-4 supports two memory architectures: distributed memory with user-level message passing communication and distributed shared memory with cache-coherent nonuniform memory access (cc-NUMA) feature. Cenju-4 system consists of from 8 to 1024 nodes connected by a multistage network which has multicast, synchronization, and gather functions. Cenju-4 adopts a Mach micro kernel based operating system, which provides several services for parallel processing. We attained 5.5 psec communication latency and 168 Mbytes/sec communication throughput an message passing communication.