Yasuyuki Miura
Shonan Institute of Technology
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Publication
Featured researches published by Yasuyuki Miura.
Communications and Network | 2013
Yasuyuki Miura; Masahiro Kaneko Kaneko; M.M. Hafizur Rahman; Shigeyoshi Watanabe
The Tori-connected mESH (TESH) Network is a k-ary n-cube networks of multiple basic modules, in which the basic modules are 2D-mesh networks that are hierarchically interconnected for higher level k-ary n-cube networks. Many adaptive routing algorithms for k-ary n-cube networks have already been proposed. Thus, those algorithms can also be applied to TESH network. We have proposed three adaptive routing algorithms—channel-selection, link-selection, and dynamic dimension reversal—for the efficient use of network resources of a TESH network to improve dynamic communication performance. In this paper, we implement these routers using VHDL and evaluate the hardware cost and delay for the proposed routing algorithms and compare it with the dimension order routing. The delay and hardware cost of the proposed adaptive routing algorithms are almost equal to that and slightly higher than that of dimension order routing, respectively. Also we evaluate the communication performance with hardware implementation. It is found that the communication performance of a TESH network using these adaptive algorithms is better than when the dimension-order routing algorithm is used.
Journal of Networks | 2009
M.M. Hafizur Rahman; Yasushi Inoguchi; Yukinori Sato; Yasuyuki Miura; Susumu Horiguchi
Interconnection networks play a crucial role in the performance of massively parallel computers. Hierarchical interconnection networks provide high performance at low cost by exploring the locality that exists in the communication patterns of massively parallel computer systems. The Tori-connected mESH (TESH) Network is a 2D-torus network of multiple basic modules, in which the basic modules are 2D-mesh networks that are hierarchically interconnected for higher level networks. In this paper, we present a deadlock-free routing algorithm for the TESH network using 2 virtual channels - 2 being the minimum number for dimension-order routing - and evaluate the networks dynamic communication performance under various nonuniform traffic patterns, using the proposed routing algorithm. We evaluate the dynamic communication performance of TESH, mesh, and torus networks by computer simulation. It is shown that the dynamic communication performance of the TESH network is better than that of the mesh and torus networks.
international conference on consumer electronics | 2015
Yasuyuki Miura; Junpei Sugioka; Naohisa Fukase
In this research, we propose the evaluation scheme of interconnection network of Network on Chip (NoC) by the approach based on probability. In this paper, we focus the multistage network for simplify, and carry out the communication performance analysis on the single flit communication. As the result, the result of flit-level simulation and probability model simulation became almost same. As future works, we will consider the model with wormhole routing and virtual channel. The goal of our research is to evaluate the performance of Link-Sharing Method.
international symposium on computing and networking | 2013
Yasuyuki Miura; Kentaro Shimozono; Shigeyoshi Watanabe; Kazuya Matoyama
A 2-D torus network is one of a most popular network in the area of parallel processing. Some algorithms have been proposed based on the turn model in past. However, most of those methods cannot be applied to torus network without modifying. In this paper, we propose the North-South First Routing (NSF Routing) which combined the North First method (NF) and the South First method (SF). NF and SF are the part of the algorithms by a Turn model. NSF Routing is applicable to 2-D Torus. Moreover, performance is evaluated by a software simulation. As a result, it was shown that a throughput improves in some communication patterns.
pacific rim conference on communications, computers and signal processing | 2011
Naohisa Fukase; Yasuyuki Miura; Shigeyoshi Watanabe
In this paper, we propose the sharing method that shares a memory between some physical link by using the multi port memory in wormhole router for NoC(Network on Chip) as efficient usage of the flit buffers. If the proposed method is implemented by conventional method, hardware cost increase greatly. Therefore, we implement proposed method by using two methods that a memory is shared by block size and a memory is controlled by list structure. In this paper, we show the effectivity of proposed method by simple estimation of hardware cost and evaluation of communication performance by software simulation.
pacific rim conference on communications, computers and signal processing | 2013
Yasuyuki Miura; Hiroshi Ninomiya; Manabu Kobayashi; Shigeyoshi Watanabe
In this paper, we propose the method for embedding the latch and the flip flop (FF) circuit to the universal logic circuit of Double Gate Carbon NanoTube Field Effect Transistor (DG-CNTFET) proposed in the previous work. Previously, 2-inputs universal logic circuit by 8 DG-CNTFET was proposed. If the embedding of flip flop to them is possible, the reconfigurable circuit which includes a state such as flip flop can be realized. The result of our research shows that SR-latch and D-latch with 3-inputs/state can be embedded within 2-inputs universal logic circuit. Thus it is shown that a D-FF can be embedded to two 2-inputs universal logic circuit.
international symposium on computing and networking | 2013
Naohisa Fukase; Yasuyuki Miura; Shigeyoshi Watanabe; M.M. Hafizur Rahman
We have proposed a memory sharing method of the wormhole routed network-on-chip architecture. In our method, a memory is shared between multiple physical links by using the multi-port memory. We evaluate and discuss the communication performance in the various situations. It is shown that the minimum number of memory banks required in multiport memory for 2D-torus and 2D-mesh networks is 8. Our proposed method yields high performance for both torus and mesh networks. Even this high performance is retained when the buffer size and the packet length are same.
international conference on consumer electronics | 2016
Weijie Zhou; Yasuyuki Miura
In this research, we propose the image correction method for low-illuminance image of the normal video camera. In the motion recognition for low-light video images which was filmed at night, it is possible to improve the accuracy of recognition by intensity correction and noise removal as preparation. It is possible to realize robust motion recognition to the changes in illumination. Therefore, in the preparation of the combination of gamma correction and denoising filter, we have to consider about the appropriate parameters. In this research, we introduce the moving-average filter as the denoising filter, and evaluate the processing time and the performance for the proposed method.
international conference on consumer electronics | 2016
Yasuyuki Miura; Taishi Sueyoshi; Takafumi Mori
In this research, we focused low illumination video image of “below 1 lux” obtained by normal type video camera, and we have considered the method of image correction for moving-object detection by inter-frame differencing. The method of this research is the combination of gamma correction and denoising as the preparation of inter-frame differencing. In this paper, F-measure was introduced as objective value, and the number of denoising was estimated by using k-means clustering. As the result, we had the feeling that the estimation using F-measure is proper. But it was shown that estimation using k-means had to be improved.
international conference on consumer electronics | 2016
Junpei Sugioka; Yasuyuki Miura
In this paper, we propose the mixture communication method of single-flit and wormhole routing. In the method, a buffer memory is shared in each link and virtual channels are assigned. We also evaluated the dynamic communication performance of proposed method. As a result, the proposed method was higher throughput than the conventional method.