Yaw-Shih Shieh

High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation

Two dimensional discrete cosine transform (DCT) and inverse DCT (IDCT) have been widely used in many image processing systems. In this paper, efficient architectures with parallel and pipelined structures are proposed to implement 8times8 DCT and IDCT processors. In which, two 8-point DCT/IDCT processors with dual-bank of SRAM (128 words) and coefficient ROM (6 words), two multiplexers, and control unit are involved. The kernel arithmetic unit (AU) is designed by using CORDIC arithmetic. The proposed architectures for 2D DCT/IDCT processors not only simplify hardware but also reduce the power consumption with high performances

An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm

Discrete Cosine transform (DCT) and inverse DCT (IDCT) have been widely used in many image processing systems and real-time computation of nonlinear time series. In this paper, a novel lineararray of DCT and IDCT is derived from the data flow of subband decompositions representing the factorized coefficient matrices in the matrix formulation of the recursive algorithm. For increasing the throughput as well as decreasing the hardware cost, the input and output data are reordered. The proposed 8-point DCT/IDCT processor with four multipliers, simple adders, and less registers and ROM storing the immediate results and coefficients, respectively, has been implemented on FPGA (field programmable gate array) and SoC (system on chip). The linear-array DCT/IDCT processor with the computation complexity and hardware complexity is fully pipelined and scalable for variable-length DCT/IDCT computations.

A Novel Fractional-Discrete-Cosine-Transform-Based Reversible Watermarking for Healthcare Information Management Systems

Digital watermarking is a good tool for healthcare information management systems. The well-known quantization-index-modulation- (QIM-) based watermarking has its limitations as the host image will be destroyed; however, the recovery of medical image is essential to avoid misdiagnosis. A transparent yet reversible watermarking algorithm is required for medical image applications. In this paper, we propose a fractional-discrete-cosine-transform- (FDCT-) based watermarking to exactly reconstruct the host image. Experimental results show that the FDCT-based watermarking is preferable to the QIM-based watermarking for the medical image applications.

Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters

This paper proposes two architectures of 2D discrete wavelet transform (DWT) and inverse DWT (IDWT). The first high-efficiency architecture comprises a transform module, an address sequencer, and a RAM module. The transform module has uniform and regular structure, simple control flow, and local communication. The significant advantages of the single transform module are fall hardware-utilization and low-power. The second architecture features parallel and pipelined computation and high throughput. Both architectures are very suitable for VLSI implementation of new-generation image coding/decoding systems, such as JPEG-2000. In the realization of 2D DWT/IDWT, we focus on a FPGA and VLSI implementation using 4-tap Daubechies filters, which saves power and reduces chip area

Haar-Wavelet-Based Just Noticeable Distortion Model for Transparent Watermark

Watermark transparency is required mainly for copyright protection. Based on the characteristics of human visual system, the just noticeable distortion (JND) can be used to verify the transparency requirement. More specifically, any watermarks whose intensities are less than the JND values of an image can be added without degrading the visual quality. It takes extensive experimentations for an appropriate JND model. Motivated by the texture masking effect and the spatial masking effect, which are key factors of JND, Chou and Li (1995) proposed the well-known full-band JND model for the transparent watermark applications. In this paper, we propose a novel JND model based on discrete wavelet transform. Experimental results show that the performance of the proposed JND model is comparable to that of the full-band JND model. However, it has the advantage of saving a lot of computation time; the speed is about 6 times faster than that of the full-band JND model.

Histogram Modification and Wavelet Transform for High Performance Watermarking

This paper proposes a reversible watermarking technique for natural images. According to the similarity of neighbor coefficients’ values in wavelet domain, most differences between two adjacent pixels are close to zero. The histogram is built based on these difference statistics. As more peak points can be used for secret data hiding, the hiding capacity is improved compared with those conventional methods. Moreover, as the differences concentricity around zero is improved, the transparency of the host image can be increased. Experimental results and comparison show that the proposed method has both advantages in hiding capacity and transparency.

A novel VLSI linear array for 2-D DCT/IDCT

This paper proposes an efficient one-dimensional (1-D) N-point discrete cosine and inverse discrete cosine transform (DCT/IDCT) architectures using sub-band decomposition algorithm. Based on the row-column decomposition technique, the two-dimensional (2-D) N×N DCT/IDCT architecture with two successive 1-D DCT/IDCT processors and one transpose memory is proposed. The orthonormal property of DCT/IDCT transformation matrices is fully used to simplify the hardware complexities. The proposed architectures with computation complexity O(5N/8) and O(3N/8) for DCT and IDCT, respectively, and low hardware complexity O(3N/8) for both DCT and IDCT are fully pipelined and scalable for variable-length 2-D DCT/IDCT computation.

Memory-Efficiency and high-speed architectures for forward and inverse DCT with multiplierless operation

Two-dimensional discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) have been widely used in many image processing systems. In this paper, efficient architectures with parallel and pipelined structures are proposed to implement 8×8 DCT and IDCT processors. In which, only one bank of SRAM (64 words) and coefficient ROM (6 words) is utilized for saving the memory space. The kernel arithmetic unit, i.e. multiplier, which is demanding in the implementation of DCT and IDCT processors, has been replaced by simple adders and shifters based on the double rotation CORDIC algorithm. The proposed architectures for 2-D DCT and IDCT processors not only simplify hardware but also reduce the power consumption with high performances.

Adaptive Binary Arithmetic Coder-Based Image Feature and Segmentation in the Compressed Domain

Image compression is necessary in various applications, especially for efficient transmission over a band-limited channel. It is thus desirable to be able to segment an image in the compressed domain directly such that the burden of decompressing computation can be avoided. Motivated by the adaptive binary arithmetic coder (MQ coder) of JPEG2000, we propose an efficient scheme to segment the feature vectors that are extracted from the code stream of an image. We modify the Compression-based Texture Merging (CTM) algorithm to alleviate the influence of overmerging problem by making use of the rate distortion information. Experimental results show that the MQ coder-based image segmentation is preferable in terms of the boundary displacement error (BDE) measure. It has the advantage of saving computational cost as the segmentation results even at low rates of bits per pixel (bpp) are satisfactory.

A Unified Algorithm for Subband-Based Discrete Cosine Transform

Discrete cosine transform (DCT) and inverse DCT (IDCT) have been widely used in many image processing systems and real-time computation of nonlinear time series. In this paper, the unified DCT/IDCT algorithm based on the subband decompositions of a signal is proposed. It is derived from the data flow of subband decompositions with factorized coefficient matrices in a recursive manner. The proposed algorithm only requires and multiplication time for -point DCT and IDCT, with a single multiplier and a single processor, respectively. Moreover, the peak signal-to-noise ratio (PSNR) of the proposed algorithm outperforms the conventional DCT/IDCT. As a result, the subband-based approach to DCT/IDCT is preferable to the conventional approach in terms of computational complexity and system performance. The proposed reconfigurable architecture of linear array DCT/IDCT processor has been implemented by FPGA.