Yee-Chia Yeo

Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology

The dependence of the metal gate work function on the underlying gate dielectric in advanced metal-oxide-semiconductor (MOS) gate stacks was explored. Metal work functions on high-κ dielectrics are observed to differ appreciably from their values on SiO2 or in vacuum. We applied the interface dipole theory to the interface between the gate and the gate dielectric of a MOS transistor and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for gate dielectrics like SiO2, Al2O3, Si3N4, ZrO2, and HfO2 were extracted. In addition, we also explain the weaker dependence of n+ and p+ polysilicon gate work functions on the gate dielectric material. Challenges for gate work function engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future MOS technology incorporating high-κ gate dielectrics.

MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations

In this paper, we explore the scaling limits of alternative gate dielectrics based on their direct-tunneling characteristics and gate-leakage requirements for future CMOS technology generations. Important material parameters such as the tunneling effective mass are extracted from the direct-tunneling characteristics of several promising high-/spl kappa/ gate dielectrics for the first time. We also introduce a figure-of-merit for comparing the relative advantages of various gate dielectrics based on the gate-leakage current. Using an accurate direct-tunneling gate-current model and specifications from the International Technology Roadmap for Semiconductors (ITRS), we provide guidelines for the selection of gate dielectrics to satisfy the projected off-state leakage current requirements of future high-performance and low-power technologies.

Direct tunneling leakage current and scalability of alternative gate dielectrics

We explore the scaling limits of alternative gate dielectrics based on their direct tunneling characteristics and gate leakage requirements for future complementary metal–oxide–semiconductor technology generations. Important material parameters such as the tunneling effective mass are extracted for several promising high-κ gate dielectrics. We also introduce a figure of merit for comparing the relative advantages of gate dielectric candidates. Using an accurate direct tunneling gate current model and specifications from the International Technology Roadmap for Semiconductors, we provide guidelines for the selection of gate dielectrics to satisfy the off-state leakage current requirements of future high-performance and low power technologies.

Effects of high-/spl kappa/ gate dielectric materials on metal and silicon gate workfunctions

The dependence of metal and polysilicon gate work-functions on the underlying gate dielectric in advanced MOS gate stacks is explored. We observe that the metal workfunctions on high-/spl kappa/ dielectrics differ appreciably from their values on SiO/sub 2/ or in a vacuum. We also show the first application of the interface dipole theory on the metal-dielectric interface and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for SiO/sub 2/, Si/sub 3/N/sub 4/, ZrO/sub 2/, and HfO/sub 2/ are extracted. In addition, we also explain the weaker dependence of n+ and p+ polysilicon gate workfunctions on the gate dielectric. Challenges for gate workfunction engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future CMOS technology incorporating high-/spl kappa/ gate dielectrics.

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.

Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs

The impact of energy quantization on gate tunneling current is studied for double-gate and ultrathin body MOSFETs. Reduced vertical electric field and quantum confinement in the channel of these thin-body devices causes a decrease in gate leakage by as much as an order of magnitude. The effects of body thickness scaling and channel crystallographic orientation are studied. The impact of threshold voltage control solutions, including doped channel and asymmetric double-gate structures is also investigated. Future gate dielectric thickness scaling and the use of high-/spl kappa/ gate dielectrics are discussed.

Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial silicon-germanium

We report the demonstration of a novel sub-100 nm CMOS technology with strained-Si/sub 0.76/Ge/sub 0.24//Si heterostructure channels formed by ultra-high-vacuum chemical-vapor-deposition (UHV-CVD). The incorporation of 24% Ge in the channel provides a 25% enhancement in PMOSFET drive current for channel lengths down to 0.1 /spl mu/m. Enhancement in NMOSFET drive current is concomitantly observed for channel lengths below 0.4 /spl mu/m.

Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel

Thin-body p-channel MOS transistors with a SiGe/Si heterostructure channel were fabricated on silicon-on-insulator (SOI) substrates. A novel lateral solid-phase epitaxy process was employed to form the thin-body for the suppression of short-channel effects. A selective silicon implant that breaks up the interfacial oxide was shown to facilitate unilateral crystallization to form a single crystalline channel. Negligible threshold voltage roll-off was observed down to a gate length of 50 nm. The incorporation of Si/sub 0.7/Ge/sub 0.3/ in the channel resulted in a 70% enhancement in the drive current. This is the smallest SiGe heterostructure-channel MOS transistor reported to date. This is also the first demonstration of a thin-body MOS transistor incorporating a SiGe heterostructure channel.

Effects of high-/spl kappa/ dielectrics on the workfunctions of metal and silicon gates

We explore the dependence of metal and polysilicon gate work functions on the underlying gate dielectric in advanced MOS transistors. The interface dipole theory is employed to explain our experimental observation that metal work functions on high-/spl kappa/ dielectrics differ appreciably from their values on SiO/sub 2/ or in vacuum. This model shows excellent agreement with original data and reported results in the literature. In addition, we also explain the weaker dependence of n/sup +/ and p/sup +/ polysilicon gate work functions on the gate dielectric. Challenges for gate work function engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future CMOS technology incorporating high-/spl kappa/ gate dielectrics.

Molybdenum as a Gate Electrode for Deep Sub-Micron CMOS Technology

Molybdenum has several properties that make it attractive as a CMOS gate electrode material. The high melting point (~2610°C) and low coefficient of thermal expansion (5×10/ oC, at 20 oC) are well suited to withstand the thermal processing budgets normally encountered in a CMOS fabrication process. Mo is among the most conductive refractory metals and provides a significant reduction in gate resistance as compared with doped polysilicon. Mo is also stable in contact with SiO2 at elevated temperatures. In order to minimize short-channel effects in bulk CMOS devices, the gate electrodes must have work functions that correspond to Ec (NMOS) and Ev (PMOS) in Si. This would normally require the use of two metals with work functions differing by about 1V on the same wafer and introduce complexities associated with selective deposition and/or etching. In this paper, the dependence of the work function of Mo on deposition and annealing conditions is investigated. Preliminary results indicate that the work function of Mo can be varied over the range of 4.0-5.0V by a combination of suitable postdeposition implantation and annealing schemes. Mo is thus a promising candidate to replace polysilicon gates in deep sub-micron CMOS technology. Processing sequences which might allow the work function of Mo to be stabilized on either end of the Si energy band gap are explored.