Yeong-Jar Chang

MRAM defect analysis and fault modeling

With the advent of system-on-chip (SOC), the demand for embedded memory cores increases rapidly. The magnetic random access memory (MRAM) is considered one of the potential candidates that replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM has a high speed and does not need high supply voltage for read/write operations, so it has the advantages of RAM and flash memory, making it a potentially good choice for SOC. The testing of MRAM, however, has not been fully investigated. In this work we classify and analyze the MRAM defects and their behavior, and propose its fault models. We have built a SPICE model of MRAM cell and performed defect injection and simulation of a real MRAM circuit. The circuit has been implemented and fabricated with a novel 0.18 m technology. The simulation results regarding the correlation between the defects and conventional fault models show that most of the defects can be covered by the stuck-at fault model. The test data based on the fabricated chips show that the stuck-at faults do cover most of the defects on the chips. However, from the experiment we also have identified two new faults, i.e., the Multi-Victims fault and Kink fault.

A memory built-in self-diagnosis design with syndrome compression

We present a memory built-in self-diagnosis (BISD) design that incorporates a fault syndrome compression scheme. We also have developed efficient faulty-word, faulty-row, and faulty-column identification methods, which have been incorporated in our new BISD design. Our approach reduces the amount of data that need to be transmitted from the chip under test to the automatic test equipment (ATE). It therefore reduces the ATE occupation time and the required ATE capture memory space. It also simplifies the analysis that has to be performed on the ATE. Simulation results for memories under various fault pattern distributions show that in most cases the data can be compressed to less than 6% of its original size.

Built-in high resolution signal generator for testing ADC and DAC

This paper presents a design of the built-in high resolution signal generator for testing analog-to-digital converter (ADC) and digital-to-analog converter (DAC). The sigma-delta demodulator scheme is used in the design to generate on-chip high accurate stimulus. We discuss the issues on the generation of all the required stimuli using the same circuitry and other issues on implementing this scheme. Our signal generator can be applied to test the embedded 13-bit ADC and DAC in asymmetry digital subscriber line system on a chip (ADSL SoC).

Fail pattern identification for memory built-in self-repair

With the advent of deep submicron technology and system-on-chip (SOC) design methodology, we are seeing on-chip memory cores to represent a growing percentage of the chip area. The yield of an SOC is usually dominated by the memory yield, so the improvement of memory yield is crucial in SOC development. In this work, we propose a built-in self-repair (BISR) scheme for memory yield improving. The novelty of our approach is that we can identify the fail patterns so that appropriate spare elements (e.g., spare rows, columns, words, or blocks) can be allocated to repair the defective memory. Some BISR methods are discussed and compared. We select the scheme that uses fewer spare elements than others given the same repair rate. The area overhead of the BISR scheme is only 2.2% for an 8K/spl times/64 memory.

A parallel built-in diagnostic scheme for multiple embedded memories

Hundreds of memory cores can be found on a typical system-on-chip (SOC) today. Diagnosing such a large number of memory cores using a conventional built-in self-test (BIST) architecture consumes too much time, as its on-chip diagnostics support is for sequential diagnosis only. In this paper, we present a memory BIST architecture with parallel diagnosis scheme. The proposed parallel built-in self-diagnosis (PBISD) scheme was developed to work with our existing memory optimization and reconfiguration (MORE) system, which configures small memory cores into the large one specified by the user, subject to the power and geometry constraints. With PBISD and MORE, memory test and diagnosis can be done in a much shorter time, and the whole system provides a good balance among test time, test power, and test hardware overhead. Experimental results show that, when compared with a conventional BISD scheme, the diagnosis time for a case with four memory cores is only 25%. Moreover, the area overhead is only 49%, as only one test pattern generator is required.

A testable BIST design for PLL

We present a testable built-in self test(BIST) design for phase-lock loop(PLL). The design can measure the clock jitter for PLL with high precision and high accuracy due to better utilization of the test integration and test subtraction techniques. Although the BIST circuit is implemented by all digital standard cells to achieve better reliability, it can even be applied to measure the analog clock jitter. Besides, for some DfT (design for test) techniques inserted to make BIST itself testable, we discuss the trade-off among area, timing, number of test patterns and fault coverage in this paper.

Embedded memory diagnostic data compression using differential address

Embedded memory diagnostics is normally done by the built-in self-diagnosis (BISD) hardware, which collects and sends the diagnostic data to the external tester. The cost of the diagnosis process highly depends on the data volume sent between the chip under test and the tester, since the transmission time and the tester capture memory are major cost factors. We propose a memory BISD design using differential addressing, as well as a method for evaluating and choosing a proper differential address level. Based on our previous work on pattern identification BISD and syndrome compression design, the proposed differential address compression scheme further reduces the diagnostic data volume. Experimental results show that the BISD design is cost-effective.

Test pattern generation and clock disabling for test time and power reduction

In this paper, we propose a novel test architecture called the pseudo-full scan (PFS) architecture to reduce test application time and power consumption simultaneously. We also present a test generation procedure to generate a set of test patterns that is suitable for the PFS architecture. The method reduces test application time and power consumption by (1) scanning only a fraction of the flip-flops, and (2) compressing the test vector sequence into a much shorter one. Experimental results show that our method has the advantages of reducing the test application time and power dissipation compared to the conventional scan methodology.