Yeoul Na

Design of Lightweight JavaScript Software Platform for the Internet of Things

Recently, the internet of things (IoT) has become increasingly attractive in many areas to realize smart worlds. JavaScript has become prevalent for IoT programming because of its familiarity with web programmers. On the other hand, JavaScript does not allow the direct control of IoT hardware due to its language limitation. This paper proposes the IoT software platform for JavaScript programming to resolve the limitation. For proof of concept, the platform based on SpiderMonkey and Raspberry Pi was implemented.

A processor-based decoupled timing controller for flexible and low-cost 2D/3D plasma display panel design

Recently PDP market has been shrinking gradually, but the expansion of 3D (3 dimensional) TV provides a new opportunity to PDP of retrieving its market share by favor of its higher response speed over LCD. In this paper, we propose a novel processor-based decoupled PDP timing controller design which is flexible, and therefore meets the design requirements, i.e., to support rapid and low cost design revision. To generate high frequency signal in real-time without any undesired latency, we adopt a decoupled architecture to the PDP timing controller. The design also supports multi-clock domain signal generation by managing multiple threads. Taking advantage of the flexibility and programmability in software execution, the design for 2D (2 dimensional) can be also easily extended to 3D design with minor modification. We implemented a prototype system of the proposed design which successfully runs on FPGA attached to 42-inch and 50-inch PDP panels with high-definition (HD) resolution. The system generates multi-clock domain timing control signals at 100 MHz and 133 MHz simultaneously and the extension for 3D design has negligible resource increments over the 2D design.

Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture

A cross call between a host processor and FPGA is one of the main challenges for supporting automatic translation of high-level languages into hardware description languages (HDL). In this paper, we present a novel communication framework between the processor and FPGA, which supports unlimited cross calls and hardware recursive calls by following the softwares frame layout in HDL code generation and sharing a stack space between software and hardware codes. Also, we introduce two implementation methods for our cross call, a direct and an indirect interfaces by an instruction-level and an interrupt communication, respectively. Our experiment shows that the proposed approach achieves our goal with small additional complexity in implementation and insignificant overhead in execution time.

The effect of Cl-doping concentration on the resistivity of polycrystalline CdZnTe:Cl thick film

Polycrystalline CdZnTe thick films were grown by thermal evaporation method using CdZnTe and CdZnTe:Cl source. We obtained polycrystalline CdZnTe thick films having high resistivity (5times10 9 Omegamiddotcm) similar that of single crystals. Cl-doped polycrystalline CdZnTe thick films(Cl: 100, 200, 300, 400 ppm) were prepared on polished graphite substrate keeping substrate temperature between 350~500 degC. The average grain size and resistivity are similar each other. This paper present the effect of Cl-doping on the resistivity of polycrystalline CdZnTe thick films.

Hierarchical data structure-based timing controller design for plasma display panels

In this paper, we propose a timing controller design to use a hierarchical structure of control signals for plasma display panels (PDPs). Also, we used a double buffering and a repeatable FIFO in order to reduce the workload of memory accesses for control data, and provided a graphical user interface program for easy control data management. Our prototype system runs at 83 MHz on Spartan-3A DSP FPGA, and the new design achieves the reduction of 73 % in resource usage from the previous implementation.

Server system modeling for data-centric computing: In terms of server specifications, benchmarks, and simulators

Server systems that support cloud, IoT (Internet of Things), content searching services, etc. are constantly increasing due to large data generation at every day, thereby maintenance cost of the servers is also becoming considerable. Therefore, it is significant to keep server systems cost efficient and provide user satisfaction by evaluating the server performance in detail. In this paper, we present important considerations of estimating the server performance, which include server specification, architectural configuration, benchmarks, and a comparison of architectural simulators.

Processor-based decoupled PDP timing controller design

This paper presents an efficient design of a processor-based PDP timing controller that supports multiple high frequency control signal channels in multi-clock domain. We implemented a prototype system using the proposed design on FPGA attached to 42-inch and 50-inch PDP panels with HD resolution.

Hardware Assisted Randomization of Data

Data-oriented attacks are gaining traction thanks to advances in code-centric mitigation techniques for memory corruption vulnerabilities. Previous work on mitigating data-oriented attacks includes Data Space Randomization (DSR). DSR classifies program variables into a set of equivalence classes, and encrypts variables with a key randomly chosen for each equivalence class. This thwarts memory corruption attacks that introduce illegitimate data flows. However, existing implementations of DSR trade precision for better run-time performance, which leaves attackers sufficient leeway to mount attacks. In this paper, we show that high precision and good run-time performance are not mutually exclusive. We present HARD, a precise and efficient hardware-assisted implementation of DSR. HARD distinguishes a larger number of equivalence classes, and incurs lower run-time overhead than software-only DSR. Our implementation achieves run-time overheads of just 6.61% on average, while the software version with the same protection costs 40.96%.

Bytecode Corruption Attacks Are Real—And How to Defend Against Them

In the continuous arms race between attackers and defenders, various attack vectors against script engines have been exploited and subsequently secured. This paper explores a new attack vector that has not received much academic scrutiny: bytecode and its lookup tables. Based on our study of the internals of modern bytecode interpreters, we present four distinct strategies to achieve arbitrary code execution in an interpreter. To protect interpreters from our attack we propose two separate defense strategies: bytecode pointer checksums and non-writable enforcement. To demonstrate the feasibility of our approach, we instantiate our attacks and proposed defense strategies for Python and Lua interpreters. Our evaluation shows that the proposed defenses effectively mitigate bytecode injection attacks with low overheads of less than 16% on average.

JavaScript Parallelizing Compiler for Exploiting Parallelism from Data-Parallel HTML5 Applications

With the advent of the HTML5 standard, JavaScript is increasingly processing computationally intensive, data-parallel workloads. Thus, the enhancement of JavaScript performance has been emphasized because the performance gap between JavaScript and native applications is still substantial. Despite this urgency, conventional JavaScript compilers do not exploit much of parallelism even from data-parallel JavaScript applications, despite contemporary mobile devices being equipped with expensive parallel hardware platforms, such as multicore processors and GPGPUs. In this article, we propose an automatically parallelizing JavaScript compiler that targets emerging, data-parallel HTML5 applications by leveraging the mature affine loop analysis of conventional static compilers. We identify that the most critical issues when parallelizing JavaScript with a conventional static analysis are ensuring correct parallelization, minimizing compilation overhead, and conducting low-cost recovery when there is a speculation failure during parallel execution. We propose a mechanism for safely handling the failure at a low cost, based on compiler techniques and the property of idempotence. Our experiment shows that the proposed JavaScript parallelizing compiler detects most affine parallel loops. Also, we achieved a maximum speedup of 3.22 times on a quad-core system, while incurring negligible compilation and recovery overheads with various sets of data-parallel HTML5 applications.