Yi-Yu Liu

Binary decision diagram with minimum expected path length

We present methods to generate a Binary Decision Diagram (BDD) with minimum expected path length. A BDD is a generic data structure which is widely used in several fields. One important application is the representation of Boolean functions. A BDD representation enables us to evaluate a Boolean function: Simply traverse the BDD from the root node to the terminal node and retrieve the value in the terminal node. For a BDD with minimum expected path length will be also minimized the evaluation time for the corresponding Boolean function. Three efficient algorithms for constructing BDDs with minimum expected path length are proposed.

Wire sizing alternative: an uniform dual-rail routing architecture

To achieve minimum signal propagation delay, the non-uniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploits the wire width flexibilities to trade area for performance. However, many additional design rules, which confine the routing flexibilities, are introduced in nanoscale circuit designs. With the increasing difficulties of fabricating nanoscale circuits, the conventional non-uniform routing architecture becomes clumsy. We propose an uniform dual-rail routing architecture to cope with these new challenges. The proposed architecture exploits the anti-Miller effect between two adjacent wires with the same signal source. Hence, the coupling capacitance between these two wires is reduced. The simulation results demonstrate that our proposed architecture provides a signal propagation channel with similar propagation delay, less crosstalk noise, and less power consumption to the conventional non-uniform routing architecture with moderate routing area overheads. In terms of the properties and the scalabilities, we argue that the uniform dual-rail routing architecture is a wire sizing alternative without incurring layout irregularity and stacked vias overheads.

An efficient hybrid LUT/SOP reconfigurable architecture

With the increasing NRE cost of advanced process technologies, reconfigurable devices receive great attention in small and medium volume IC designs. However, lower logic utilization and slower timing performance limit the efficacy of FPGA and CPLD. In this paper, we propose an efficient hybrid LUT/SOP reconfigurable design style to exploit both the advantages of LUT-cell and SOP-cell for circuit design. After that, architectural evaluations are performed in order to have the best cell mixture ratio. Furthermore, three logic optimization techniques, cell collapsing, phase flipping, and phase duplication, are proposed for hybrid LUT/SOP FPGA synthesis from a pure LUT-based design. The experimental results demonstrate that our proposed hybrid LUT/SOP design style achieves 35% circuit performance improvement and 51% transistor count reduction as compared with the depth optimal 4-LUT-based FPGA.

Crosstalk-Aware Domino-Logic Synthesis

We propose a logic synthesis flow which utilizes the functionality of circuit to synthesize a domino-cell network which will have more wires crosstalk-immune to each other. For that purpose, techniques of output phase flipping and crosstalk-aware technology mapping are used. Meanwhile, metric to measure the crosstalk sensitivity of domino cells in synthesis level is proposed. Experimental results demonstrate that the crosstalk sensitivity of the synthesized domino-cell network is greatly reduced by 51% using our synthesis flow as compared with conventional methodology. Furthermore, after placement and routing are performed, the ratio of the number of crosstalk-immune wire pairs to the number of total wire pairs is about 25% using our methodology as compared to 9% using conventional techniques

Dual-addressing memory architecture for two-dimensional memory access patterns

Cache performance is an important factor in modern computing systems due to large memory access latency. To exploit the principle of spatial locality, a requested data set and its adjacent data sets are often loaded from memory to a cache block simultaneously. However, the definition of adjacent data sets is strongly correlated with the memory organization. Commodity memory is a two-dimensional structure with two (row and column) access phases to locate the requested data set. Therefore, the adjacent data sets are neighbors of the requested data set in a linear order. In this paper, we propose a novel memory organization with dual-addressing modes as well as orthogonal memory access mechanisms. Our dual-addressing memory can be efficiently applied to two-dimensional memory access patterns. Furthermore, we propose a cache coherence protocol to tackle the cache coherence issue due to synonym data set of the dual-addressing memory. For benchmark kernels with two-dimensional memory access patterns, the dual-addressing memory achieves 60% performance improvement as compared to conventional memory. Both cache hit rate and cache utilization are improved after removing two-dimensional memory access patterns from conventional memory.

Dangling-wire avoidance routing for crossbar switch structured ASIC design style

In the routing architecture of a structured ASIC, crossbar is one of the most area efficient switch blocks. Nevertheless, dangling-wire occurs when there is a routing bend in crossbar switch. The dangling-wire incurs longer wire length as well as higher interconnection capacitance. In this paper, we are motivated to tackle dangling-wire routing issues for structured ASIC. We first propose a compact graph model for crossbar switch routing. With our graph model, switch connectivity relations can be removed to keep the 2-D structured ASIC routing graph efficient and to speed up run-time of our routing algorithm. Furthermore, we leverage state-of-the-art techniques into our routing framework, which contains deferred pin assignment, Steiner point re-assignment, and anchor pair insertion, to minimize dangling-wires taking both total wire length and routing congestion into account. The experimental results demonstrate that our proposed routing framework greatly reduces 21% dangling-wires, 34% channel width, and 13% total wire length as compared with VPR using crossbar switch.

Crosstalk minimization in logic synthesis for PLAs

We propose a maximum crosstalk effect minimization algorithm that takes logic synthesis into consideration for PLA structures. To minimize the crosstalk effect, a technique for permuting wire is used which contains the following steps. First, product terms are partitioned into long and short sets, and then the product terms in the long and short sets are interleaved. After that, we take advantage of the crosstalk immunity of product terms in the long set to further reduce the maximum coupling capacitance of the PLA. Finally, synthesis techniques such as local and global transformations are taken into consideration to search for a better result. The experiments demonstrate that our algorithm can effectively minimize the maximum coupling capacitance of a circuit by 51% as compared with the original area-minimized PLA without crosstalk effect minimization.

A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements

We propose a cache architecture using a 7T/14T SRAM (Fujiwara et al., 2009) and a control mechanism for reliability enhancements. Our control mechanism differs from conventional dynamic voltage-frequency scaling (DVFS) methods in that it considers not only the cycles per instruction behaviors but also the cache utilization. To measure cache utilization, a novel metric is proposed. The experimental results show that our proposed method achieves 1000 times less bit-error occurrences compared with conventional DVFS methods under the ultralow-voltage operation. Moreover, the results indicate that our proposed method surprisingly not only incurs no performance and energy overheads but also achieves on average a 2.10% performance improvement and a 6.66% energy reduction compared with conventional DVFS methods.

Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style

In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the same pre-fabricated device and wire masks. Nevertheless, the interconnection delay in a pre-fabricated wire slows down circuit performance as a result of high capacitive load. We propose a dual-rail routing architecture that reduces wire delay by 10% to 15% compared to the original routing architecture. Furthermore, we propose a dual-rail insertion algorithm to reduce routing area overhead. The experimental results demonstrate that our dual-rail technique reduces wire delay by 9.8% with 4.8% routing area overhead and improves overall circuit performance by 7.0%.

Buffer design and optimization for lut-based structured ASIC design styles

The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split off a long wire into several buffered wire segments for circuit performance improvement. In this paper, we are motivated to investigate the buffer insertion issues in LUT-based structured ASIC design style. We design the layouts of two dedicated buffers and extract the technology dependent parameters for evaluations. After that, we propose a channel migration technique, which employs both intra-channel migration and inter-channel migration, to alleviate the sub-channel saturation problem. The experimental results demonstrate that dedicated buffers are essential for structured ASIC design style.