Yifeng Liu

Analysis of EMP Coupling to a Device from A Wire Penetrating a Cavity Aperture Using Transient Electromagnetic Topology

This paper studies an electromagnetic pulse coupling to a device from a wire penetrating a cavity aperture by applying the transient electromagnetic topology (TEMT) method. The computation process is divided into two steps: The three dimensional finite-difference time-domain (FDTD) method is used to compute the excitation fields of the wire, and then the SPICE model of the wire is used to compute the current response of the device. The results obtained by the TEMT method are compared with those obtained numerically by using the FDTD method only and experimentally. And good agreement has been obtained. All the calculations are done in the time domain, and the TEMT method can be used to directly analyze nonlinear or time-varying loads. The wire does not have to be meshed in the TEMT method, so the TEMT method is more efficient than the FDTD method only.

Spice Simulation and Experimental Study of Transmission Lines with TVSs Excited by EMP

This paper presents the experimental study and SPICE simulation of transmission lines without or with transient voltage suppressors (TVSs) radiated by a fast rise-time electromagnetic pulse. TVSs are usually attached to transmission lines to protect terminal loads from surge interferences. The currents of the terminal loads and TVSs are obtained experimentally and numerically by using the SPICE circuits of transmission lines and TVSs. The results show that the induced energy dissipated through one termination will become larger when a TVS is attached to the other termination of the transmission line. And experimental results reveal that TVSs can provide protection for the loads, but the protection effectiveness may be not enough against fast rise-time surges.

Distributed Automatic Voltage Control framework for large-scale wind integration in China

Three critical cascading faults with nearly 2000 WTGs (Wind Turbine Generator) tripped took place in China on early 2011, from which the reactive power and voltage control issues for large wind farms are spotlighted. Some key factors inducing the cascading trip are surveyed by this paper firstly, including WTGs voltage distribution, dynamic reactive power reserves and coordination of tight-coupled wind farms. Rather than only focusing on the PCC (Point of Common Coupling) voltage, AVC (Automatic Voltage Control) in a wind farm is actually a network-based control considering voltage distribution and drop on the radial feeders. A hierarchical control AVC (Automatic Voltage Control) framework considering wind farms integration is presented and the detailed functions are introduced, involving network model, state estimation, 3-D visualization based monitoring, power flow & sensitivity calculation, security assessment & early warning and control strategy decision. Such an AVC system has been applied into several wind farms, one of which is selected as an example to introduce the configuration and deployment details. The distributed AVC system is also a mini-EMS (Energy Management System) prototype for large wind farms.

Development of a low noise readout ASIC for CZT detectors for gamma-ray spectroscopy applications

A multi-channel readout ASIC for pixelated CZT detectors has been developed for gamma-ray spectroscopy applications. Each channel consists of a low noise dual-stage charge sensitive amplifier (CSA), a CR-(RC)4 semi-Gaussian shaper and a class-AB output buffer. The equivalent noise charge (ENC) of input PMOS transistor is optimized for 5 pF input capacitance and 1 μs peaking time using gm/ID design methodology. The gain can be adjusted from 100 mV/fC to 400 mV/fC and the peaking time can be adjusted from 1 μs to 4 μs. A 16-channel chip has been designed and fabricated in 0.35 μm 2P4M CMOS technology. The test results show that the chip works well and fully satisfies the design specifications. The ENC was measured to be 72 e + 26 e/pF at 1 μs peaking time and 86 e + 20 e/pF at 4 μs peaking time. The non-uniformity of the channel gain and ENC was less than ±12% and ±11% respectively for 16 channels in one chip. The chip was also tested with a pixelated CZT detector at room temperature. The measured energy resolution at 59.5 keV photopeak of 241Am and 122 keV photopeak of 57Co were 4.5% FWHM and 2.8% FWHM for the central area pixels, respectively.

The digital penalized LMS deconvolution method for TPC X-ray polarimeter signal processing

This article presents the Digital Penalized LMS (Least Mean Square) deconvolution method for processing the X-ray polarimeter readout electronics output signal. The deconvolution filter is used to recover the detector signal high frequency component, which is lost due to the limited bandwidth of the readout electronics. The DPLMS deconvolution method does not need to know the transfer function of the readout electronics system in advance and can restrain the deconvolution noise by using a noise constraint. In this paper, this method will be applied to process the simulation data generated by GEANT4 and the resulting photoelectron angular resolution of a X-ray polarimeter will be presented.

The development of a readout ASIC for TPC based X-ray polarimeter

A dedicated readout ASIC has been developed for a TPC based X-ray polarimeter. It consists of a charge sensitive preamplifier, a CR-RC shaper and a 64-cell switched capacitor array (SCA) for each channel. The signal charge distribution along the time axis can be extracted from the recorded waveforms. The first prototype has been implemented in two separate chips: the front-end part and the SCA part. The front-end part consists of a charge sensitive preamplifier and a CR-RC shaper with a peaking time of 25 ns. Simple digital signal processing algorithm such as de-convolution can be easily applied. The SCA structure is adopted for its low power consumption. The sampling frequency and the resolution is designed to be above 20MSPS (Mega-samples per Second) and 10bit, respectively. High density MOS capacitors are used for storing the samples. Careful biasing and readout scheme are used to reduce the non-linearity caused by the voltage-dependent capacitance. The SCA has differential current outputs and can be readout at 40MHz. Each ASIC has integrated 32 channels and is fabricated in a 0.18μm CMOS process. The preliminary test results show that both chips are fully functional. The noise of the front-end has been measured to be 455.2e+70.43e/pF. The write control logic of the SCA can work at 50MHz. The typical noise of a cell in the SCA is 1.25mV, meaning the static readout resolution of 9.6 bit. A maximum INL of the connected two chips is 0.27%.

Development of a current-mode ASIC for MRPC detectors

A fully current-mode front-end ASIC, named CAD has been developed for MRPC detectors for TOF applications. It consists of a current mirror preamplifier and a current discriminator for each channel. Current mode circuits can easily achieve high bandwidth and are suitable for low power supply design. A simplified circuit model has been introduced to analyze the timing performance of the current discriminator. 20 ps time jitter can be achieved for 40 fC input signal by simulation. The time jitter dramatically decreases as signal amplitude increases. A 4-channel prototype ASIC has also been designed and fabricated in a 0.35 μm CMOS technology. The chip has been evaluated with MRPC detector. The total time jitter of 184 ps has been measured.

A sub-10ps resolution current discriminator for timing applications

This paper uses a fully current-mode preamplifier and discriminator to get the accurate timing signal. The current discriminator has different mechanism from a voltage discriminator and hence its time resolution is dependent on both of the bandwidth and circuit gain. Detailed analysis will be present in the paper. The ASIC has been designed and tested with signals with different rise times and amplitudes. The result can verify the analysis that time jitter can be reduced by increasing the circuit gain. 10ps time resolution has been measured for signals with 2.5ns in rise time and only ~20μA above the threshold current.

CAD-II: the second version current-mode readout ASIC for high-resolution timing measurements

This paper presents the second version of a fully current-mode front-end ASIC, CAD (Current Amplifier and Discriminator), for MRPC detectors for TOF applications. Several upgrades have been made in this new version, including: 1). Using differential input stages with input impedance down to 30 Ω and LVDS compatible outputs; 2). Much higher current gain and bandwidth of 4.5 A/A and 380 MHz; 3). Fabricated in 0.18 μ m CMOS process instead of 0.35 μ m CMOS technology used in CAD-I. The detailed design of the ASIC will be described as well as the measurement results. The single-ended input impedance could be as low as 32 Ω and the power consumption was measured to be 15 mW per channel. Input referred RMS noise current was about 0.56 μ A. The threshold could be set as low as 4.5 μ A referred to input, corresponding to 9 fC for the typical MRPC detector signal with 2 ns width. Sub-10 ps resolution has been measured for input signal above 200 μ A.

CASCA: A readout ASIC for a TPC based X-ray polarimeter

The paper presents a prototype ASIC (CASCA: Charge Amplifier with Switched Capacitor Array) for a TPC based X-ray Polarimeter (XTP). It measures two dimensional photoelectron tracks generated by the incident X-ray photons with one dimensional strip readout. The other dimension is calculated by the drift time from the signal waveform. In order to achieve 100 μm track resolution fine pitch strips are used, requiring high density readout electronics with 20 MSPS waveform sampling capability. CASCA integrates 32 channel full function signal processing circuits and is fabricated in a 0.18μm CMOS process. Each channel consists of a charge sensitive preamplifier, a CR-RC shaper with a peaking time of 25 ns, a baseline holder, a discriminator and a 64-cell switched capacitor array (SCA). The analog front-end and the SCA circuits have been implemented and verified in two separate chips in the previous prototypes. Several modifications have also been made, such as using native NMOS capacitor to store the samples and changing the structure of the switched capacitor circuits. The test results of CASCA show that the equivalent noise charge (ENC) is about 1500e with 14.5pF input capacitance. The INL (Integrated Nonlinearity) is better than 0.6% and the center-of-gravity time jitter has been measured to be no more than 3 ns.