Yih-Lang Li

Multi-threaded collision-aware global routing with bounded-length maze routing

Modern global routers use various routing methods to improve routing speed and the quality. Maze routing is the most time-consuming process for existing global routing algorithms. This paper presents two bounded-length maze routing (BLMR) algorithms (optimal-BLMR and heuristic-BLMR) to perform much faster routing than traditional maze routing algorithms. The proposed sequential global router, which adopts a heuristic-BLMR, identifies less-wirelength routing results with less runtime than state-of-the-art global routers. This study also proposes a parallel multi-threaded collision-aware global router based on a previous sequential global router. Unlike the conventional partition-based concurrency strategy, the proposed algorithm uses a task-based concurrency strategy. Experimental results reveal that the proposed sequential global router uses less wirelength and runs about 1.9X to 18.67X faster than other state-of-the-art global routers. Compared to the proposed sequential global router, the proposed parallel global router yields almost the same routing quality with average 2.71 and 3.12-fold speedup on overflow-free and hard-to-route benchmarks, respectively, when running on an Intel quad-core system.

NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing

The increasing complexity of interconnection designs has enhanced the importance of research into global routing when seeking high-routability (low overflow) results or rapid search paths that report wirelength estimations to a placer. This work presents two routing techniques, namely circular fixed-ordering monotonic routing and evolution-based rip-up and rerouting using a two-stage cost function in a high-performance congestion-driven 2-D global router. We also propose two efficient via-minimization methods, namely congestion relaxation by layer shifting and rip-up and reassignment, for a dynamic programming-based layer assignment. Experimental results demonstrate that our router achieves performance similar to the first two winning routers in ISPD 2008 Routing Contest in terms of both routability and wirelength at a 1.05 × and 18.47 × faster routing speed. Moreover, the proposed layer assignment achieves fewer vias and shorter wirelength than congestion-constrained layer assignment (COLA).

NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing

Modern global routers employ various routing methods to improve routing speed and quality. Maze routing is the most time-consuming process for existing global routing algorithms. This paper presents two bounded-length maze routing (BLMR) algorithms (optimal-BLMR and heuristic-BLMR) that perform much faster routing than traditional maze routing algorithms. In addition, a rectilinear Steiner minimum tree aware routing scheme is proposed to guide heuristic-BLMR and monotonic routing to build a routing tree with shorter wirelength. This paper also proposes a parallel multithreaded collision-aware global router based on a previous sequential global router (SGR). Unlike the partitioning-based strategy, the proposed parallel router uses a task-based concurrency strategy. Finally, a 3-D wirelength optimization technique is proposed to further refine the 3-D routing results. Experimental results reveal that the proposed SGR uses less wirelength and runs faster than most of other state-of-the-art global routers with a different set of parameters , , , . Compared to the proposed SGR, the proposed parallel router yields almost the same routing quality with average 2.71 and 3.12-fold speedup on overflow-free and hard-to-route cases, respectively, when running on a 4-core system.

TRIAD: a triple patterning lithography aware detailed router

TPL-friendly detailed routers require a systematic approach to detect TPL conflicts. However, the complexity of conflict graph (CG) impedes directly detecting TPL conflicts in CG. This work proposes a token graph-embedded conflict graph (TECG) to facilitate the TPL conflict detection while maintaining high coloring-flexibility. We then develop a TPL aware detailed router (TRIAD) by applying TECG to a gridless router with the TPL stitch generation. Compared to a greedy coloring approach, experimental results indicate that TRIAD generates no conflicts and few stitches with shorter wirelength at the cost of 2.41× of runtime.

Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing

The increasing complexity of interconnection designs has enhanced the importance of research into global routing when seeking high-routability (low overflow) results or rapid search paths that report wire-length estimations to a placer. This work presents two routing techniques, namely adaptive pseudorandom net-ordering routing and evolution-based rip-up and reroute using a two-stage cost function in a high-performance congestion-driven 2-D global router. We also propose two efficient via-minimization methods, namely congestion relaxation by layer shifting and rip-up and re-assignment, for a dynamic programming-based layer assignment. Experimental results demonstrate that our router achieves performance similar to the first two winning routers in ISPD 2008 Routing Contest in terms of both routability and wire length at a 1.42X and 25.84X faster routing speed. Besides, our layer assignment yields 3.5% to 5.6% fewer vias, 2.2% to 3.3% shorter wirelength and 13% to 27% less runtime than COLA.

NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation

The implicit-connection-graph-based router is superior to the tile-based router in terms of routing graph construction and point querying. However, the implicit connection graph has a higher degree of routing graph complexity. In this paper, a new multilayer implicit-connection-graph-based gridless router called NEMO is developed. Unlike the first implicit-connection-graph-based router that embeds all routing layers onto a routing plane, NEMO constructs a routing plane for each routing layer. Additionally, each routing plane comprises tiles, not an array of grid points with their connecting edges, and consequently, the complexity of the routing problem decreases. Each grid point then represents exactly one tile or its left-bottom corner such that a tile query is equivalent to any point query inside the queried tile, and a grid maze becomes tile propagation. Furthermore, to accelerate path search, continuous space tiles are combined as a pseudo maximum horizontally or vertically stripped tile. Experimental results reveal that NEMO conducts a point-to-point path search around ten times faster than the implicit-connection-graph-based router. General-purpose routing by NEMO also improves routing performance by approximately 1.69times-55.82 times, as compared to previously published works based on a set of commonly used MCNC benchmark circuits

Double patterning lithography aware gridless detailed routing with innovative conflict graph

Double patterning lithography (DPL) is the most feasible solution for sub-32nm nodes owing to the recurrent delay in next generation lithography. DPL attempts to decompose a single layer of one layout into two masks in order to increase pitch size and improve depth of focus (DOF). Considering DPL at detailed routing stage can improve the flexibility of layout decomposition as compared to the post-routing layout decomposition. The conflict graph proposed in [8] provides a global view of all nets in a layout to obtain a highly decomposable layout with less yield loss. However, adopting conflict graph in routing process using grid-based model or gridless model both brings huge overhead. This work presents an innovative conflict graph (ICG) to realize adopting conflict graph in a routing process. Three routing-friendly characteristics of ICG are constant-time conflict cycle detection, lazy ICG update, and light-weight routing overhead. To efficiently utilize routing resources for a crowded region, gridless models provide a better solution space than grid-based models do. This work also develops, to our knowledge, the first DPL-aware gridless detailed routing with ICG to generate a highly decomposable routing result. Moreover, greedily assigning colors for routed nets may cause unnecessary stitches or even a coloring conflict. This work presents a deferred coloring assignment-based routing flow to escape local optimum of a greedy coloring approach. Experimental results indicate that DPL-aware routing results contain no coloring conflicts, and the stitches produced by the proposed router are less than those produced by a greedy coloring approach by 41% on average with only 0.22% and 30% increment in wirelength and runtime, respectively.

An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow

Engineering change order (ECO) routing is frequently requested in the later design stage for the purpose of delay and noise optimization. ECO routing is complicated as a result of huge existing obstacles and the requests for various design rules. The tile-based routing model results in fewer nodes of the routing graph than grid and connection-based routers; however, the number of nodes of the tile-based routing graph has grown to over a billion for system-on-chip designs, while no notable progress has been achieved in the routing speed of the tile-based router since it was proposed. This paper first proposes a novel routing graph reduction (RGR) method for promoting tile propagation speed and then depicts a new ECO routing design flow with RGR and enhanced global routing flow (EGRF). RGR can be used to remove redundant tiles as well as align and merge neighboring tiles in order to diminish tile fragmentation such that the tile-based ECO router can run twice as fast while still producing an optimal path. Compared with a commercial placement and routing tool, the proposed tile-based router with RGR obtains better routing performance and routing quality for three ECO routings. EGRF incorporates ECO global routing considering via-resource congestion metric with extended routing and global cell (GCell) restructuring to prevent routing failure in routable designs. The ECO router with the proposed design flow can perform up to 20 times faster than the original tile-based router at the cost of only a slight decline in routing quality. Experimental results also demonstrate that a more congested layout tends to have higher graph reduction rate. Also discussed herein are further refinements by dynamic weighting of via and wire resources based on the vacancy density of the routed design and further application of RGR to multiple-net routing

Density-aware Detailed Placement with Instant Legalization

Placement consists of three stages: global placement, legalization, and detailed placement (DP). Recently, most research works have concentrated on improving global placement and legalization, but innovations in DP have been rarely seen. ICCAD13 held a DP contest that formulates the emerging placement issues into a bin-utilization metric and maximum cell displacement constraint. This paper presents a detailed placer that can effectively reduce both half-perimeter wirelength and the peak bin-utilization under the displacement constraint. The proposed lazy-update based incremental density profit function supports efficient cell swapping. Combination of lazy-update density profit function and Density-Driven Swap lets our placer achieve AOFP of 0 for the majority of the ICCAD13 test cases. The placer presented produces the best placement results among the top3 teams in the ICCAD13 contest.

Optimization of placement solutions for routability

Routability has become a critical issue in VLSI design flow. To avoid producing an unroutable design, many placers [47] invoke global routers to get a congestion map and then move cells to reduce congestion based on this map. However, as cells move, the accuracy of the congestion map degrades, thereby affecting the effectiveness of the placer in minimizing congestions. Moreover, most global routers [8-13] ignore local congestion. If placers are guided by these routers, it may produce hard-to-route placement solutions in terms of detailed routing. This work develops a routability optimizer, called Ropt, to reduce both global and local routing congestion levels of a given placement. Based on a local-routability-aware routing model, Ropt builds a global routing instance to obtain global and local congestion information for guiding global re-placement. In addition, this work presents a new legalization scheme to preserve the global routing instance after legalization. Finally, local detailed placement further minimizes the local congestion and wirelength. For the evaluation of Ropt, we use an academic global router and a commercial router to obtain both global and detailed routing results, respectively. Experimental results reveal that Ropt can improve the routing quality (in terms of congestion, wirelength, and violation) and routing runtime of a given placement solution.