Yili Gu

Study of the contour-based optical proximity correction methodology

As design rule continues to shrink, resolution enhancement techniques (RET) such as optical proximity correction (OPC) become more and more complex to enable design printability. As we know, typically integrated circuit (IC) layouts are simple shapes such as rectangles. However, high spatial frequency components of the mask spectrum that are not captured by the low-pass pupil result in a rounded image. In addition, the diffusion process in the postexposure bake (PEB) step makes the wafer rounding effects worse. This means that it is difficult to get the wafer image to match the design exactly at corners, even with the most aggressive OPC methodology. Therefore, pre-OPC site placement optimization is necessary to achieve high quality wafer images. In this work, a contour-based OPC methodology is proposed to minimize the time consumption in pre-OPC simulation site placement optimization and OPC job running. Rounded target contours that best describe the real intended wafer result are used as the target during OPC correction. By comparing classical OPC recipe-driven target point placement and contour-based OPC methodology, it is found that contour-based OPC methodology can achieve comparable image quality in a shorter turn around time (TAT) with fewer engineer resources.

Depth of focus enhancement for sub-110-nm technology by using KrF double-exposure lithography

Traditional double-exposure lithography (DEL) or double-patterning lithography (DPL) methodologies stem most from the resolution enhancement standpoint. A single mask with high feature densities is split into two exposure steps, each with lower feature densities that can be easily resolved. The DEL is proposed as the process window enhancement technology for sub-110-nm technology. Features with sparse pitches are printed by a first step of dense pitch exposures and a second exposure with dummy features removed. The pattern decomposition strategy described is similar to that of subresolution assisting features (SRAF). So it is compatible with the traditional rule-based SRAF implementation methodology. By comparing the depth of focus (DOF) of the 110-nm lithography process between the single exposure and the double exposure, it is found that the DOF for marginal features is extended by using double-exposure methodology, and thus extends the capability of KrF exposure tools. Furthermore, the link between the overlay performance and the overlap of the second exposures trim slots over the first exposure is studied. The results show that the overlay control is within the KrF scanner capability. As a further study, the proposed double-exposure methodology for the 90-nm lithography process is evaluated.

Contour-based optical proximity correction

Due to the corner rounding effect in litho process, it is hard to make the wafer image as sharp as the drawn layout near two-dimensional pattern in IC design1, 2. The inevitable gap between the design and the wafer image make the two-dimensional pattern correction complex and sensitive to the OPC correction recipe. However, there are lots of different two-dimensional patterns, for example, concave corner, convex corner, jog, line-end and space-end. Especially for Metal layer, there are lots of jogs are created by the rule-based OPC. So OPC recipe developers have to spend lots to efforts to handle different two-dimensional fragment with their own experience. In this paper, a general method is proposed to simplify the correction of two-dimensional structures. The design is firstly smoothed and then simulation sites are move from the drawn layer to this new layer. It means that the smoothed layer is used as OPC target instead of the drawn Manhattan pattern. Using this method, the OPC recipe tuning becomes easier. In addition, the convergence of two-dimensional pattern is also improved thus the runtime is reduced.

Hybrid Sub-Resolution Assisting Feature Implementation Methodology by Process Window Aware Optical Proximity Correction Model

Driven by steadily decreasing critical dimensions in the semiconductor technology, sub-resolution assisting feature (SRAF) has been proposed to enlarge the capability of the exposure technique to smaller pitch requirements exceeding the standard lithography specification by improving the through-focus process window. There are generally two types of SRAF implementation methodologies: the rule-based approach and the model-based approach. In this paper, the hybrid SRAF implementation methodology is proposed to benefit from these two methodologies. Firstly, the candidate rules are selected by using the process window aware optical proximity correction (OPC) model. Secondly, the candidate SRAF rules are taped out. Finally, the optimized candidates among the taped out SRAF rules are verified by wafer data. If the wafer data show that the SRAF rule will not meet the criteria, the SRAF implementation methodology will go back to evaluate other candidates. From the wafer data, it is proved that the hybrid SRAF implementation methodology can achieve an optimized through-focus process window in a short turn around time (TAT) with lower engineering and mask cost.

Layout optimization for thick-film resist overlay metrology

Design for Manufacturing (DFM) is being widely accepted as one of the keywords in cutting edge lithography and OPC technologies. DFM solutions impact the design-to-silicon flow at various stages, often during different time-point in the product life cycle, and often with both process equipments and metrology tools. As the design rule shrinks and mask field size increases, tighter specifications are applied on non-critical layers, including thick implant resist typically with thickness of 3.0um and above. Various functions, as Enhanced Global Alignment (EGA), Super Distortion Matching (SDM), and Grid Compensation for Matching (GCM), are widely used to achieve improved overlay accuracy. However, poor uniformity for CD and overlay was observed for thick resist implant layers. Systematic uncorrectable overlay residue was observed from the overlay map. Cross-section analysis shows asymmetric resist profile existed, causing inaccurate signal reading during the measurement. Although there are some recent researches focusing on CD-SEM metrology of overlay residue, overlay tools in current foundries are mainly optical-based ones, which are limited by the optical resolution. Instead of locally focusing on the manufacturing, an innovative methodology is proposed in this paper, by applying the newly designed overlay marks to solve this manufacturing problem. From the comparison of overlay performances between the proposed layout and the original design, it is shown that the taper asymmetry induced errors are significantly reduced.