Yizhuang Xie

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array—application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

Real-Time Spaceborne Synthetic Aperture Radar Float-Point Imaging System Using Optimized Mapping Methodology and a Multi-Node Parallel Accelerating Technique

With the development of satellite load technology and very large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. A key goal of the on-board SAR imaging system design is to achieve high real-time processing performance under severe size, weight, and power consumption constraints. This paper presents a multi-node prototype system for real-time SAR imaging processing. We decompose the commonly used chirp scaling (CS) SAR imaging algorithm into two parts according to the computing features. The linearization and logic-memory optimum allocation methods are adopted to realize the nonlinear part in a reconfigurable structure, and the two-part bandwidth balance method is used to realize the linear part. Thus, float-point SAR imaging processing can be integrated into a single Field Programmable Gate Array (FPGA) chip instead of relying on distributed technologies. A single-processing node requires 10.6 s and consumes 17 W to focus on 25-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. The design methodology of the multi-FPGA parallel accelerating system under the real-time principle is introduced. As a proof of concept, a prototype with four processing nodes and one master node is implemented using a Xilinx xc6vlx315t FPGA. The weight and volume of one single machine are 10 kg and 32 cm × 24 cm × 20 cm, respectively, and the power consumption is under 100 W. The real-time performance of the proposed design is demonstrated on Chinese Gaofen-3 stripmap continuous imaging.

A novel word length optimization method for radix-2 k fixed-point FFT

Dear editor, Fast Fourier transform (FFT) is one of the most fundamental algorithms used in digital signal processing. Many applications such as orthogonal frequency division multiplexing (OFDM), long term evolution (LTE), and ultra-wideband (UWB) systems require an area efficient, high accuracy FFT processor. To design a high-precision and lowcomplexity FFT/IFFT processor architecture, the optimum bit sizing technique in each stage is usually adopted. Many fixed-point pipeline FFT processors are designed in previous studies [1–5]. However, most of the word length schemes in these studies are proposed based on long-time fixedpoint simulation. It is difficult to provide an accurate, fast word length scheme because of the diversity of FFT algorithms and the complexity of circuit structure. In this letter, we focus on the widely-used radix-2 decimation-in-frequency (DIF) fast Fourier transform (FFT) algorithm. Based on our previous research on fixed-point FFT signal-to-quantization-noise ratio (SQNR) assessment [6], the analytical expression of the word length in different stages is deduced. We further put forward a word length optimization method based on the analytical expression. In our previous work [6], we reached an SQNR analytical expression of radix-2 fixed-point FFT. We re-list the output SQNR expression as follows:

A Unified Reconfigurable CORDIC Processor for Floating-Point Arithmetic

Abstract: This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximizes the sharing of common hardware circuit and achieves the area-delay-efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 1638416384 points target Synthetic Aperture Radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T FPGA platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.

An FPGA-Accelerated Doppler Parameters Estimation Engine for Real-Time Synthetic Aperture Radar Imaging System

In this paper, we demonstrate an achievable implementation of Doppler parameters estimation engine. Taking advantage of FPGA, a highly parallelized and reconfigurable structure with a unified calculation is adopted. We build a prototype using single off-the-shelf Xilinx XC6VSX315T FPGA to verify the proposed method in a 16384 ×16384 SAR imaging process. The experiment result can achieve more than 20x time speedups over CPU-based solution, and the FPGA hardware resources can be balanced.

A high performance digital signal processor for monopulse tracking radar

In order to meet the crucial requirements of system miniaturization and low power consumption, a high performance digital signal processor for monopulse tracking radar application applying linear frequency modulation (LFM) signal is given. The system functions are partitioned into several time-division stages with software or hardware implementation methods, and then an optimized prototype system and the on-chip processing structure based on system on chip (SoC) concept are respectively proposed and implemented. In our case, the field programmable gate array (FPGA) chip is adopted to integrate all the processing algorithms invoked in the monopulse tracking radar. In the final verification section, the field experimental results fully prove the validity and engineering applicability of the digital signal processor.

Finite word length optimization for spaceborne SAR imaging systems

Synthetic Aperture Radar (SAR) system provides two-dimensional (range and azimuth), high-resolution radar images for various geological prospecting applications. Due to its high computational demands, most of the SAR imaging systems, either airborne or spaceborne, can only do offline processing, especially for spaceborne scenarios. Techniques based on Field Programmable Gate Arrays (FPGAs) provide a potential solution that satisfies all the computing constraints. However, to implement an entire SAR imaging processing system using floating-point arithmetic on FPGA is inefficient. One of the most challenging problem when using fixed-point processing is how to optimize the word length and reduce the impact of fixed-point errors on resolution. In this paper, we theoretically analyze the finite word length computing errors for SAR imaging system, and propose a mathematical error model. Then, an asymptotically optimal expression of the system level output noise-to-signal ratio is derived. Based on the expression, we apply the proposed methodology to various SAR imaging algorithms such as Range Doppler (RD) and Chirp Scaling (CS) algorithms. To validate the proposed method, we implement a SAR imaging system on an FPGA based platform. The run-time results show that the proposed method can achieve a usable image quality assessed by metrics such as Integrated Side Lobe Ratio (ISLR), Peak Side Lobe Ratio (PSLR) and Relative Mean Square Deviation (RMSD).