Yo Yamaguchi

An L-band ultra-low-power-consumption monolithic low-noise amplifier

A low-power consumption variable-gain low-noise amplifier (LNA) is demonstrated. To achieve low noise, low distortion, and low power consumption simultaneously, a cascode connection between an enhancement-mode GaAs MESFET (EFET) and a depletion-mode GaAs MESFET (DFET) is employed. The EFET is superior to the DFET in its gain and noise figure performance while the DFET offers good intermodulation distortion performance. The advantages of both types of FETs are combined in the developed LNA. It shows excellent performance with an NF of 2.0 dB, a gain of 12.2 dB, and an IP/sub 3/ of 5.1 dBm at 1.9 GHz. The demonstrated performance satisfies the specifications of the Japanese Personal Handyphone System even at the ultra-low power consumption of 2.0 mW. >

A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique

A complete direct digital synthesizer (DDS) using a self-adjusting phase-interpolation technique is fabricated using 0.35-/spl mu/m CMOS process technology. A self-adjusting delay generator reduces the periodic jitter in the most significant bit (MSB) of the accumulator in this DDS. To improve the spectral performance, a method of spurious signal reduction that uses offset current sources (OCSs) is newly adopted in the delay generator. Test results confirm that the delay generator produces highly accurate delay timing without the need to adjust circuit constants. The measured spurious free dynamic range (SFDR) is 62 dBc for a dc to 10-MHz output and the power consumption of the complete DDS is 39.2 mW at a 100-MHz clock rate.

Wide-band SSB subharmonically pumped mixer MMIC

To achieve low conversion-loss and high image-rejection performance in the wide band for up and down conversion, an SSB subharmonically pumped mixer using an in-phase RF divider/combiner is proposed. The SSB mixer MMIC is integrated in a small area of 1.8/spl times/1.3 mm/sup 2/ and shows good performance in the range 21.6 to 30.8 GHz.

A highly integrated quasi-millimeter wave receiver chip using 3D-MMIC technology

A highly integrated quasi-millimeter wave receiver chip that integrates 22 circuits on a 3 x 2.3 mm chip using three-dimensional MMIC (3D-MMIC) technology is presented. The receiver MMIC operates with an LO signal in the 2.7-3.1 GHz range. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.4 GHz. It can use low-cost VCOs and demodulators in a 2-3 GHz frequency band. The power dissipation of the MMIC is only 450 mW. It also achieved low noise (3.4 dB) and high gain (41 dB) at 26 GHz. Furthermore, it achieved a high dynamic range using two step attenuators in the RF and IF frequency bands with a new built-in inverter using an N-channel depression FET.

1.9 GHz-band low voltage and low power consumption RF IC chip-set for personal communications

New RF circuit techniques have overcome the distortion problems for low supply voltages. The RF IC chip-set for the 1.9 GHz Japanese personal handy phone (PHP) system includes a low noise amplifier (GaAs MMIC), a mixer (GaAs MMIC), a linear power amplifier (GaAs MMIC), a T/R switch (GaAs MMIC), a 1.9 GHz direct-conversion quadrature modulator (Si LSI), and a frequency synthesizer (Si LSI). These components achieve very low power consumption at very low supply voltages such as 2.0 to 2.4 V.<<ETX>>

Broadband Low Noise Amplifier with High Linearity for Software-Defined Radios

We propose a broadband low noise amplifier with high linearity performance. The amplifier achieves broadband, low noise performance and high linearity using a bias circuit with high impedance. The bias circuit consists of an inductor, a resistor, and a current source. The circuit obtains high impedance using a high resistive component. From 0.8 to 5 GHz, the low noise amplifier shows an S21 of 20plusmn1 dB and an Sll of less than -9 dB. The noise figure is 1.5-2.7 dB for frequencies from 0.5 to 5 GHz. The output 1-dB compression point at 2 GHz is +6.3 dBm.

Miniaturized Multilayer Inductors on GaAs Three-dimensional MMIC

Newly developed multi-layer inductors on GaAs three-dimensional MMICs are presented. We tested single-, double-, triple-, and quadruple-layer stacked-type inductors in what may be the first report on inductors on a GaAs MMIC with three or more layers. These proposed multilayer inductors can produce higher inductance in the same area as conventional 2D-MMICs. The performance of the single-and multilayer inductors was measured on wafer and calculated by electromagnetic field analysis using the finite element method. Though they are the same size, the multilayer inductors produce 2~11 times higher inductance than the single-layer inductors. In addition, the degradation of the multilayer inductor performances, such as resistance, Q-factor and self-resonant frequency, was not seen compared with the single-layer inductors. Multilayer inductors make it possible to shrink circuit size from many hundreds of MHz to the millimetre wave.

A Highly Integrated X-band Frequency Quadrupler MMIC using 3D-MMIC Technology

A highly integrated X-band frequency quadrupler MMIC using three-dimensional MMIC (3D-MMIC) technology is presented. It consists of four amplifiers, two doublers, and a 2-band elimination filter. These seven circuits are integrated on only a 2.25 mm times 1.05 mm chip. The third and fifth harmonic components, which are spurious components nearest to the desired component, are well suppressed. The desired/undesired ratio is about 40 dB. The MMIC supplies +5 dBm of the fourth harmonic component at input power as low as -10 dBm. The power dissipation of the MMIC is only 160 mW.

A Highly Integrated Quasi-millimeter Wave Transmitter MMIC Using 3D-MMIC Technology

A highly integrated quasi-millimeter-wave transmitter MMIC that integrates 26 circuits in a 3 mm times 3 mm area using three-dimensional MMIC (3D-MMIC) technology is presented. The power dissipation of the MMIC is only 0.54 W. It achieved a high P1 dB of 6 dBm and gain of 19 dB at 26 GHz. Furthermore, it integrated step attenuators with a new built-in inverter using an N-channel depression FET for transmit power control.

A non-binary direct digital synthesizer with an extended phase accumulator

We describe a new direct digital synthesizer (DDS) in which output tuning resolution is flexibly controlled. The new DDS has an extended phase accumulator (EPA) controlled by two frequency control words; one determines the wave number within a single EPA operation cycle, and the other determines the length of the cycle. The EPA allows the DDS to provide jitter-free signals, the frequencies of which are given by arbitrary fractional expressions. (The denominator is fixed in conventional DDS that use normal phase accumulators.) Experimental results showed that the EPA worked well, allowing flexible output tuning resolution.