Yoann Blancquaert

Diffraction based overlay and image based overlay on production flow for advanced technology node

One of the main challenges for lithography step is the overlay control. For the advanced technology node like 28nm and 14nm, the overlay budget becomes very tight. Two overlay techniques compete in our advanced semiconductor manufacturing: the Diffraction based Overlay (DBO) with the YieldStar S200 (ASML) and the Image Based Overlay (IBO) with ARCHER (KLA). In this paper we will compare these two methods through 3 critical production layers: Poly Gate, Contact and first metal layer. We will show the overlay results of the 2 techniques, explore the accuracy and compare the total measurement uncertainty (TMU) for the standard overlay targets of both techniques. We will see also the response and impact for the Image Based Overlay and Diffraction Based Overlay techniques through a process change like an additional Hardmask TEOS layer on the front-end stack. The importance of the target design is approached; we will propose more adapted design for image based targets. Finally we will present embedded targets in the 14 FDSOI with first results.

Target design optimization for overlay scatterometry to improve on-product overlay

Scatterometry mark design for improvement of the metrology performance is investigated in this joint work by ASML and STMicroelectronics. The studied marks are small, enabling metrology within the device area. The new mark-design approach reduces the effects from the mark-edges during the metrology measurement. For this, small assist-features are integrated in the mark design on the wafer. Thereby the new designs: 1. enlarge the metrology measurement-window, 2. optimize the repeatability and accuracy of the metrology at given mark size, 3. allow added functionality to existing marks within the current mark area, such as monitoring process asymmetry or multiple layer information, 4. allow for mark miniaturization at equal performance, enabling intra-field positioning. With this metrology tool-optical proximity correction (MT-OPC) included in the mark design, the metrology window is enhanced, while improved on-product overlay performance is obtained.

Performance of ASML YieldStar μDBO overlay targets for advanced lithography nodes C028 and C014 overlay process control

Continued tightening of overlay control budget in semiconductor lithography drives the need for improved metrology capabilities. Aggressive improvements are needed for overlay metrology speed, accuracy and precision. This paper is dealing with the on product metrology results of a scatterometry based platform showing excellent production results on resolution, precision, and tool matching for overlay. We will demonstrate point to point matching between tool generations as well as between target sizes and types. Nowadays, for the advanced process nodes a lot of information is needed (Higher order process correction, Reticle fingerprint, wafer edge effects) to quantify process overlay. For that purpose various overlay sampling schemes are evaluated: ultra- dense, dense and production type. We will show DBO results from multiple target type and shape for on product overlay control for current and future node down to at least 14 nm node. As overlay requirements drive metrology needs, we will evaluate if the new metrology platform meets the overlay requirements.

Process development of a maskless N40 via level for security application with multi-beam lithography

The maskless electron beam lithography system, based on massively parallel electron-beam writing strategy has the ability for low-cost production of truly unique individual chips in volume manufacturing, compatible with optical systems. Mapper Lithography has introduced the FLX-1200 platform installed at CEA-Leti. This paper will present fully process-integration stepwise developments to be compliant with the single via layer demanding targets based on dual damascene process: The lithographic performances and etch transfer optimization were firstly evaluated on a layer stack representative of N40 CMOS technology by developing step-by-step approach: - 1/ Trilayer lithography of via layer and partial etch into low-k development with VSB 50kV - 2/ Litho/etch process of product wafer with VSB 50keV - 3/ Trilayer lithography of via pattern and etch into low-k for FLX-1200 multi-beam 5kV - 4/ last litho of via pattern on product wafer using FLX (no etch yet). In addition, the overlay and CDU capability of FLX-1200 are assessed for via 3, and the alignment to product wafer is tested. Via patterning integration showing the up-to-date achievements is mature enough to start first customer demos for security application.

Scatterometry control for multiple electron beam lithography

The evaluation of scatterometry for monitoring intended variations in innovative scatterometry targets that mimic nonuniformities potentially caused by multibeam Maskless Lithography (MEB-ML2) is presented. Specialized scatterometry targets consisting of lines and spaces were produced that have portions exposed using the nominal, or POR (Process of Record), dose, and portions exposed with a slightly different dose. These exposure plans created targets with different line CDs (critical dimensions). Multiple target designs were implement, each with a different combination of magnitude of CD shift and size of the region containing lines with a shifted CD. The scatterometry, or OCD (Optical Critical Dimension), spectra show clear shifts caused by the regions with shifted CD, and trends of the scatterometry results match well with trends of the estimated CD as well as the trends produced by measurements using a critical dimension scanning electron microscope (CD-SEM) system. Finally, the OCD results are correlated to the CD-SEM measurements. Taking into account resist morphology variations across the wafer, correlations between OCD and CD-SEM of the weighted average CD across the various targets are shown to be very good. Correlations are done using the rigorous TMU analysis methodology. Due to the different targeted CD values within each scatterometry structure, a new methodology for estimating the error of the CD-SEM measurements for nominally non-uniform targets is presented.

Performance validation of Mapper's FLX-1200

Mapper has installed its first product, the FLX–1200, at CEA-Leti in Grenoble (France). This is a maskless lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. The FLX-1200, containing 65,000 parallel electron beams in a 13mm x 2mm electron optics slit, is capable of patterning any resolution and any different type of structure all the way down to 28 nm node patterns. As of August 2017 the FLX-1200 has a fully operational electron optics column, including a 65,000 beam blanker. In this paper the latest technical achievements of the FLX-1200 have been described: beam current is at 80% of FLX-1300 target (85 minutes per wafer). For 42nm hp dense lines a CDu of 8nm 3σ and a LWR of 5nm 3σ has been demonstrated. The stitching error is 12nm μ+3σ and regarding overlay a 15nm capability demonstrated, provided matching strategy is implemented and the mirror map is calibrated.

Programmed LWR metrology by multi-techniques approach

Nowadays, roughness control presents a huge challenge for the lithography step. For advanced nodes, this morphological aspect reaches the same order of magnitude than the Critical Dimension. Hence, the control of roughness needs an adapted metrology. In this study, specific samples with designed roughness have been manufactured using e-beam lithography. These samples have been characterized with three different methodologies: CD-SEM, OCD and SAXS. The main goal of the project is to compare the capability of each of these techniques in terms of reliability, type of information obtained, time to obtain the measurements and level of maturity for the industry.

Performance validation of Mapper FLX-1200

Operating maskless, massively parallel electron beam direct write (MEBDW) is an attractive alternative to optical lithography in micro and nano device manufacturing. Mapper Lithography develops MEBDW tools able to pattern wafers, for application nodes down to 28nm, with a throughput around one wafer per hour. A prototype tool from this series, named FLX-1200, is installed in the CEA-Leti clean room. This paper reviews the current performances of this prototype and the methodology used to measure them. On standardized exposure, consisting of 100 fields of 5×5mm2 exposed, in less than one hour, on 300mm silicon wafers, we obtained CD uniformity below 10nm (3σ) and LWR of 4.5nm for 60nm half pitch dense lines. We also demonstrate capability of 15nm and 25nm (3σ) for stitching and overlay errors respectively.

Feasibility of monitoring a multiple e-beam tool using scatterometry and machine learning: stitching error detection

Multiple electron beam direct write lithography is an emerging technology promising to address new markets, such as truly unique chips for security applications. The tool under consideration, the Mapper FLX-1200, exposes long 2.2 μm-wide zones called stripes by groups of 49 beams. The critical dimensions inside and the registration errors between the stripes, called stitching, are controlled by internal tool metrology. Additionally, there is great need for on-wafer metrology of critical dimension and stitching to monitor Mapper tool performance and validate the internal metrology. Optical Critical Dimension (OCD) metrology is a workhorse technique for various semiconductor manufacturing tools, such as deposition, etching, chemical-mechanical polishing and lithography machines. Previous works have shown the feasibility to measure the critical dimension of non-uniform targets by introducing an effective CD and shown that the non-uniformity can be quantified by a machine learning approach. This paper seeks to extend the previous work and presents a preliminary feasibility study to monitor stitching errors by measuring on a scatterometry tool with multiple optical channels. A wafer with OCD targets that mimic the various lithographic errors typical to the Mapper technology was created by variable shaped beam (VSB) e-beam lithography. The lithography process has been carefully tuned to minimize optically active systematic errors such as critical dimension gradients. The OCD targets contain horizontal and vertical gratings with a pitch of 100 nm and a nominal CD of 50 nm, and contain various stitching error types such as displacement in X, Y and diagonal gratings. Sensitivity to all stitching types has been shown. The DX targets showed non-linearity with respect to error size and typically were a factor of 3 less sensitive than the promising performance of DY targets. A similar performance difference has seen in nominally identical diagonal gratings exposed with vertical and horizontal lines, suggesting that OCD metrology for DX cannot be fully characterized due to lithography errors in gratings with vertical lines.

Manufacturing of roughness standard samples based on ACF/PSD model programming

Currently, Line Edge Roughness (LER) and Line Width Roughness (LWR) control presents a huge challenge for the lithography step in microelectronic industries. For advanced nodes, this morphological aspect reaches the same order of magnitude than the Critical Dimension, which leads to an increased power consumption by transistors and devices. Hence, the control of roughness needs an adapted metrology. This study proposes to manufacture roughness standard samples and their validation. These samples can be used as standards to evaluate the capabilities of several tools. The preliminary part of this study has been carried out with periodical roughness sample to demonstrate the metrology approach. Further, programming of roughness based on Power Spectral Density (PSD) with Auto-Correlation Function (ACF) model is used to achieve roughness close to the real roughness case. A description of how design programmed roughness has been made and its exposition in the real conditions are detailed in this study. Moreover, a specific methodology of control has been developed, the results obtained have been compared with design inputs and mostly validated by experimental processes. This work represents the first step of manufacturing roughness standard samples based on PSD model design.