Yogendra Joshi

Thermal Challenges in Next-Generation Electronic Systems

Thermal challenges in next-generation electronic systems, as identified through panel presentations and ensuing discussions at the workshop, Thermal Challenges in Next Generation Electronic Systems, held in Santa Fe, NM, January 7-10, 2007, are summarized in this paper. Diverse topics are covered, including electrothermal and multiphysics codesign of electronics, new and nanostructured materials, high heat flux thermal management, site-specific thermal management, thermal design of next-generation data centers, thermal challenges for military, automotive, and harsh environment electronic systems, progress and challenges in software tools, and advances in measurement and characterization. Barriers to further progress in each area that require the attention of the research community are identified.

Visualization of droplet departure on a superhydrophobic surface and implications to heat transfer enhancement during dropwise condensation

Droplet departure frequency is investigated using environmental scanning electron microscopy with implications to enhancing the rate of dropwise condensation on superhydrophobic surfaces. Superhydrophobic surfaces, formed by cupric hydroxide nanostructures, allow the condensate to depart from a surface with a tilt angle of 30° from the horizontal. The resulting decrease in drop departure size shifts the drop size distribution to smaller radii, which may enhance the heat transfer rate during dropwise condensation. The heat transfer enhancement is estimated by modifying the Rose and Le Fevre drop distribution function to account for a smaller maximum droplet size on a superhydrophobic surface.

Thermal issues in next-generation integrated circuits

The drive for higher performance has led to greater integration and higher clock frequency of microprocessor chips. This translates into higher heat dissipation and, therefore, effective cooling of electronic chips is becoming increasingly important for their reliable performance. We systematically explore the limits for heat removal from a model chip in various configurations. First, the heat removal from a bare chip by pure heat conduction and convection is studied to establish the theoretical limit of heat removal from a bare die bound by an infinite medium. This is followed by an analysis of heat removal from a packaged chip by evaluating the thermal resistance due to individual packaging elements. The analysis results allow us to identify the bottlenecks in the thermal performance of current generation packages, and to motivate lowering of thermal resistance through the board-side for efficient heat removal to meet ever increasing reliability and performance requirements.

Melting in a side heated tall enclosure by a uniformly dissipating heat source

Melting of an organic phase change material (PCM) n-triacontane (C30H62) in a side heated tall enclosure of aspect ratio 10, by a uniformly dissipating heat source has been studied computationally and experimentally. While heat transfer data for melting in enclosures under isothermal wall boundary condition are available in the literature, other boundary conditions, such as constant heat flux often arise in applications of PCM for transient thermal management of electronics. An implicit enthalpy–porosity approach was utilized for computational modeling of the melting process. Experimental visualization of melt front locations was performed. Comparisons between experimental and computational heat transfer data and melt interface locations were good. Fluid flow and heat transfer characteristics during melting suggested that natural convection plays a dominant role during initial stages of melting. At later times, the strength of natural convection diminishes as melting is completed. Correlations of heat transfer rate and melt fraction with time were obtained.

Experimental and Numerical Study of a Stacked Microchannel Heat Sink for Liquid Cooling of Microelectronic Devices

One of the promising liquid cooling techniques for microelectronics is attaching a microchannel heat sink to, or directly fabricating microchannels on, the inactive side of the chip. A stacked microchannel heat sink integrates many layers of microchannels and manifold layers into one stack. Compared with single-layered microchannels, stacked microchannels provide larger flow passages, so that for a fixed heat load the required pressure drop is significantly reduced. Better temperature uniformity can be achieved by arranging counterflow in adjacent microchannel layers. The dedicated manifolds help to distribute coolant uniformly to microchannels. In the present work, a stacked microchannel heat sink is fabricated using silicon micromachining techniques. Thermal performance of the stacked microchannel heat sink is characterized through experimental measurements and numerical simulations. Effects of coolant flow direction, flow rate allocation among layers, and nonuniform heating are studied. Wall temperature profiles are measured using an array of nine platinum thin-film resistive temperature detectors deposited simultaneously with thin-film platinum heaters on the backside of the stacked structure. Excellent overall cooling performance (0.09 ° C/W cm 2 ) for the stacked microchannel heat sink has been shown in the experiments. It has also been identified that over the tested flow rate range, counterflow arrangement provides better temperature uniformity, while parallel flow has the best performance in reducing the peak temperature. Conjugate heat transfer effects for stacked microchannels for different flow conditions are investigated through numerical simulations. Based on the results, some general design guidelines for stacked microchannel heat sinks are provided.

High-speed visualization of boiling from an enhanced structure

Abstract Using high-speed photography (1500 frames/s) bubble growth data on microporous structures immersed in a pool of dielectric coolant (FC-72) were obtained. Wafer dicing and wet etching was used to fabricate a net of interconnected microchannels on a 10 mm ×10 mm piece of silicon wafer. The resultant structure has pores that communicate the interior of microchannels to the liquid pool. The pore diameter was varied in a range 0.12–0.20 mm and the pore pitch in 0.7–1.4 mm. The data were collected maintaining the system pressure at one atmosphere and increasing the wall superheat up to 12 K. Among the geometrical parameters, the pore diameter was found to be most influential on the bubble departure diameter. The findings about the bubble growth rate, the bubbling frequency, and the bubble site density were largely in accord with the previously reported data. However, the coverage of wider ranges of wall superheat and the structural parameters in the present study revealed new bubble characteristics that was used in implementing an analytical model for boiling heat transfer on the porous structure.

Modeling of data center airflow and heat transfer: State of the art and future trends

An assessment of the current thermal modeling methodologies for data centers is presented, with focus on the use of computational fluid dynamics and heat transfer as analysis tools, and model validation. Future trends in reduced or compact modeling of data center airflow and heat transfer are presented to serve as an overview of integrating rack-level compact models into full-scale facility level numerical computations. Compact models can be used to efficiently model data centers through varying model fidelity across length scales. Dynamic effects can be included to develop next-generation control schemes to maximize data center energy efficiency.

Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional Integrated Circuits With Nonuniform Heat Flux

It is now widely recognized that the three-dimensional (3D) system integration is a key enabling technology to achieve the performance needs of future microprocessor integrated circuits (ICs). To provide modular thermal management in 3D-stacked ICs, the interlayer microfluidic cooling scheme is adopted and analyzed in this study focusing on a single cooling layer performance. The effects of cooling mode (single-phase versus phase-change) and stack/layer geometry on thermal management performance are quantitatively analyzed, and implications on the through-silicon-via scaling and electrical interconnect congestion are discussed. Also, the thermal and hydraulic performance of several two-phase refrigerants is discussed in comparison with single-phase cooling. The results show that the large internal pressure and the pumping pressure drop are significant limiting factors, along with significant mass flow rate maldistribution due to the presence of hot-spots. Nevertheless, two-phase cooling using R123 and R245ca refrigerants yields superior performance to single-phase cooling for the hot-spot fluxes approaching ∼300 W/cm 2 . In general, a hybrid cooling scheme with a dedicated approach to the hot-spot thermal management should greatly improve the two-phase cooling system performance and reliability by enabling a cooling-load-matched thermal design and by suppressing the mass flow rate maldistribution within the cooling layer.

PARAMETRIC NUMERICAL STUDY OF FLOW AND HEAT TRANSFER IN MICROCHANNELS WITH WAVY WALLS

Wavy channels were investigated in this paper as a passive scheme to improve the heat transfer performance of laminar fluid flow as applied to microchannel heat sinks. Parametric study of three-dimensional laminar fluid flow and heat transfer characteristics in microsized wavy channels was performed by varying the wavy feature amplitude, wavelength, and aspect ratio for different Reynolds numbers between 50 and 150. Two different types of wavy channels were considered and their thermal performance for a constant heat flux of 47 W/cm 2 was compared. Based on the comparison with straight channels, it was found that wavy channels can provide improved overall thermal performance. In addition, it was observed that wavy channels with a configuration in which crests and troughs face each other alternately (serpentine channels) were found to show an edge in thermal performance over the configuration where crests and troughs directly face each other. The best configuration considered in this paper was found to provide an improvement of up to 55% in the overall performance compared to microchannels with straight walls and hence are attractive candidates for cooling of future high heat flux electronics.

Design and performance evaluation of a compact thermosyphon

Thermosyphons are a promising option for cooling of high heat dissipating electronics. In this paper, the first known implementation of a compact two-phase thermosyphon for cooling of a microprocessor in a commercial desktop computer is presented. The implemented thermosyphon involves four components in a loop: an evaporator with a boiling enhancement structure, a rising tube, a condenser and a falling tube. The performance of the thermosyphon with water and PF5060 as working fluids, and the effect of inclination are studied experimentally under laboratory conditions. Experimental observations are also made at actual operating conditions to monitor the thermal behavior with changes in power output of the microprocessor. The inside cabinet of the desktop computer is also numerically simulated to understand the airside performance of the condenser.