Yokesh Kumar

Building a Communication Bridge with Mobile Hubs

We study scenarios where mobile hubs are charged with building a communication bridge between two given points s and t. We introduce a new bi-criteria optimization problem where the objectives are minimizing the number of hubs on the bridge and either the maximum or the total distance traveled by the hubs. For a geometric version of the problem where the hubs must move onto the line segment [s,t], we present algorithms which achieve the minimum number of hubs while remaining within a constant factor of a given motion constraint.

An External Memory Circuit Validation Algorithm for Large VLSI Layouts

The circuit represented by a layout must be validated by comparing it to a schematic circuit to show that the functionality is same as intended. This done by testing for graph isomorphism between the layout and schematic circuit graphs. Circuits designed currently are so large that their corresponding data structures often exceed available main memory and thus, memory hierarchy issues like disk I/Os cannot be ignored. We present an I/O efficient procedure for testing graph isomorphism between circuit graphs. Our approach is based on the global partitioning and local matching phases along with deletion of matched vertices and we give an I/O efficient procedure for each of these phases

External memory layout vs. schematic

The circuit represented by a VLSI layout must be verified by checking it against the schematic circuit as an important part of the functional verification step. This involves two central problems of matching the circuit graphs with each other (graph isomorphism) and extracting a higher level of circuit from a given level by finding subcircuits in the circuit graph (subgraph isomorphism). Modern day VLSI layouts contain millions of devices. Hence the memory requirements of the data structures required by tools for verifying them become huge and can easily exceed the amount of internal memory available on a computer. In such a scenario, a program not aware of the memory hierarchy performs badly because of its unorganized input/output operations (I/Os) as the speed of a disk access is about a million times slower than accessing a main memory location. In this article, we present I/O-efficient algorithms for the graph isomorphism and subgraph isomorphism problems in the context of verification of VLSI layouts. Experimental results show the need and utility of I/O-efficient algorithms for handling problems with large memory requirements.

Reducing EPL Alignment Errors for Large VLSI Layouts

A leading candidate for next generation lithography at sub-micron levels is electron projection lithography (EPL). EPL uses very thin membranes on which layout features are placed. To provide rigidity to this thin membrane, support structures called struts are built into membrane which divide the membrane and layout into uniform sub-fields. These sub-fields must be stitched back together on the wafer by EPL process. Alignments errors are possible during the stitching back stage. To minimize these stitching errors, minimum number of layout features must be cut while partitioning the layout into sub-fields. This problem was identified and formulated by Tang et al. in ICCAD 2002 (Tang et al., 2002). However, all the proposed algorithms take O(N2) time and space in the worst case where N is the size of input. In this paper we present an improved O(N log N) solution to the mask layout partitioning for EPL process. The algorithm presented is found to be very fast on experimental data