Yong-Jo Ahn

Implementation of fast HEVC encoder based on SIMD and data-level parallelism

This paper presents several optimization algorithms for a High Efficiency Video Coding (HEVC) encoder based on single instruction multiple data (SIMD) operations and data-level parallelism. Based on the analysis of the computational complexity of HEVC encoder, we found that interpolation filter, cost function, and transform take around 68% of the total computation, on average. In this paper, several software optimization techniques, including frame-level interpolation filter and SIMD implementation for those computationally intensive parts, are presented for a fast HEVC encoder. In addition, we propose a slice-level parallelization and its load-balancing algorithm on multi-core platforms from the estimated computational load of each slice during the encoding process. The encoding speed of the proposed parallelized HEVC encoder is accelerated by approximately ten times compared to the HEVC reference model (HM) software, with minimal loss of coding efficiency.

Study of decoder complexity for HEVC and AVC standards based on tool-by-tool comparison

High Efficiency Video Coding (HEVC) is the latest standardization efforts of ISO/IEC MPEG and ITU-T VCEG for further improving the coding efficiency of H.264/AVC standard. It has been reported that HEVC can provide comparable subjective visual quality with H.264/AVC at only half bit-rates in many cases. In this paper, decoder complexities between HEVC and H.264/AVC are studied for providing initial complexity estimates of the HEVC decoder compared with the H.264/AVC decoder. For this purpose, several selected coding tools including intra prediction, motion compensation, transform, loop filters and entropy coder have been analyzed in terms of number of operations as well as their statistical differences.

Complexity model based load-balancing algorithm for parallel tools of HEVC

Load balancing algorithm supporting parallel tools for HEVC encoder is proposed in this paper. Standardization of HEVC version 1 was finalized and which is known that its RD performance is two times better than H.264/AVC which was the most efficient video coder. However, computational complexity of HEVC encoding process derived from variable block sizes based on hierarchical structure and recursive encoding structure should be dealt as a prerequisite for technique commercialization. In this paper, basic performances of slice- and tile-level parallel tools adopted in HEVC are firstly presented and load balancing algorithm based on complexity model for slices and tiles is proposed. For four slices and four tiles cases, average time saving gains are 12.05% and 3.81% against simple slice- and tile-level parallelization, respectively.

Statistical Characteristics and Complexity Analysis of HEVC Encoder Software

In this paper, we analyzed statistical characteristics and complexity of HEVC encoder as a leading research of acceleration, optimization and parallelization. Computational complexity of the HEVC encoder is approximately twice the compression performance compared to H.264/AVC. But, the increase of encoder complexity remains a problem to be solved in the future. Before performing the research on acceleration, optimization and parallelization to reduce high complexity of HEVC encoder, we measure the complexity each module for HEVC encoder using it`s reference software HM 7.1. We also measured the predicted complexity of fast HEVC encoder software, used in real applications, using HM 7.1 applying fast encoding method. The complexity is measured in terms of the operating cycle of the encoder software under the common test sequences and conditions in the Windows PC environment. In addition, we analyze statistical characteristics of HEVC encoder software according to encoding structures and limitation using coded bitstreams.

Performance Analysis of HEVC Parallelization Methods for High-Resolution Videos

Several parallelization methods that can be applied to High Efficiency Video Coding (HEVC) decoders are evaluated. The market requirements of high-resolution videos, such as Full HD and UHD, have been increasing. To satisfy the market requirements, several parallelization methods for HEVC decoders have been studied. Understanding these parallelization methods and objective comparisons of these methods are crucial to the real-time decoding of high-resolution videos. This paper introduces the parallelization methods that can be used in HEVC decoders and evaluates the parallelization methods comparatively. The experimental results show that the average speed-up factors of tile-level parallelism, wavefront parallel processing (WPP), frame-level parallelism, and 2D-wavefront parallelism are observed up to 4.59, 4.00, 2.20, and 3.16, respectively.

Analysis of Screen Content Coding Based on HEVC

In this paper, the technical analysis and characteristics of screen content coding (SCC) based on High efficiency video coding (HEVC) are presented. For SCC, which is increasingly used these days, HEVC SCC standardization has been proceeded. Technologies such as intra block copy (IBC), palette coding, and adaptive color transform are developed and adopted to the HEVC SCC standard. This paper examines IBC and palette coding that significantly impacts RD performance of SCC for screen content. The HEVC SCC reference model (SCM) 4.0 was used to comparatively analyze the coding performance of HEVC SCC based on the HEVC range extension (RExt) model for screen content.

Intra Block Copy Analysis to Improve Coding Efficiency for HEVC Screen Content Coding

This paper describes and analyzes IBC (intra block copy) in HEVC (high efficiency video coding) SCC (screen content coding) to improve the coding efficiency of IBC. HEVC SCC reference software SCM 2 is employed to analyze the selection ratio of IBC which is newly adopted in HEVC SCC, and the tools for IBC such as the block vector prediction and block vector coding method are evaluated. Experimental results show the average IBC selection ratio is 31.08% and 0.33% in I-Slice and B-Slice, respectively. Based on this results, the coding efficiency of IBC could be improved by utilizing IBC selectively. In addition, analysis tests of block vector prediction and the block vector coding method show the current methods are not efficient to screen content videos, and the analysis results are presented to improve these methods.

Fast mode decision and early termination based on perceptual visual quality for HEVC encoders

This paper presents an early termination and fast mode decision for the HEVC encoder with a perceptual visual quality. For early termination of residual quad-tree, if the predicted errors for a transform block are not visible in terms of perceptual quality, the block is coded as the all-zero block and the transforms for the block and smaller blocks are skipped in RDO process. In addition, when a coding mode in the RDO-based mode decision stage is satisfactory in terms of visual quality, the coding mode is selected and the remaining coding modes requiring more bits are skipped. The proposed fast encoding algorithm is designed by pruning many coding modes when the coding errors with a coding mode having a small number of bits are not perceived by the human visual system. In addition, the proposed perceptual quality-based fast encoding algorithms can work with the existing objective quality-based fast decision algorithms. We found that the proposed algorithm can achieve 1.77 times acceleration of HM-16.8 with minimal perceptual visual degradation and objective quality distortion.

Layered Coding Method for Scalable Coding of HDR and SDR videos

In this paper, we propose a scalable coding method for high dynamic range (HDR) and standard dynamic range (SDR) videos based on Scalable High Efficiency Video Coding (SHVC). The proposed method has multi-layer coding architecture that consists of base layer for SDR videos and enhancement layer for HDR videos to support the backward compatibility with legacy codec and display devices. Also, to improve coding efficiency of enhancement layers, a global inverse tone mapping is applied to the reconstructed SDR video and the compensated frames are referred for coding of the enhancement layer. The proposed method is found to achieve BD-Rate gain of 43.0% on average (maximum 76.3%) for the enhancement layer and 15.7% on average (maximum 31%) for dual-layer against the SHM 7.0 reference software.

Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders

This work proposes several intrinsics on a reconfigurable processor intended for HEVC decoding and software pipelining algorithms with a coarse-grained array (CGA) architecture as well as the proposed intrinsic instructions. Software pipelining algorithms are developed for the CGA acceleration of inverse transform, pixel reconstruction, de-blocking filter and sample adaptive offset modules. To enable efficient software pipelining, several very-long instruction-word-based intrinsics are designed in order to maximize the parallelization rather than the computational acceleration. We found that the HEVC decoder with the proposed intrinsics yields 2.3 times faster in running clock cycle than a decoder that does not use the intrinsics. In addition, the HEVC decoder with CGA pipelining algorithms executes 10.9 times faster than that without the CGA mode.