Yong-seok Lee

Floating Body DRAM Characteristics of Silicon-On-ONO (SOONO) Devices for System-on-Chip (SoC) Applications

We completed the demonstration of three key functions of SOONO devices by demonstrating the DRAM characteristics of FD and PD SOONO devices successfully, together with the previously reported logic transistor and flash memory characteristics. Floating body SOONO DRAM cells implemented on electrically thin buried insulator shows the large sensing margins more than 5muA in FD device with long data retention and nondestructive read even at the W/L of 60/55nm which is the smallest IT DRAM ever reported.

4-Bit Double SONOS Memories (DSMs) Using Single-Level and Multi-Level Cell Schemes

In this article, we report improved results of 4-bit double SONOS memories (DSMs) with 4-storage nodes through the optimization of ONO layer thicknesses for front and back sides. They show more balanced characteristics between the front and back channels, higher VTH shifts above 2.4V, larger read margins above 1.6V, better endurance, and longer retention time than our previous results. In addition, we also propose and demonstrate a highly scaled 4-bit DSM using multi-level technology. The VTH shifts above 4V splitting into 4 levels without noticeable interferences are achieved. Each nodes show clear 4 levels with good retention

122 Mb High Speed SRAM Cell with 25 nm Gate Length Multi-Bridge-Channel MOSFET (MBCFET) on Bulk Si Substrate

As a part of continued multi-bridge-channel MOSFET (MBCFET) study, we have successfully fabricated 122Mb SRAM cell with 25 nm gate length CMOS MBCFET on bulk Si wafers. The 6-T MBCFET SRAM cell shows high static noise margin (SNM) of 320 mV at Vcc= 0.8 V. Using tall-embedded-gate (TEG) and source/drain (S/D) engineering, 2.6times105 times on/off current ratio and 3.46 mA/mum of on-state current at 13 nA/um of off-state current were achieved. In addition, triple-bridge-channel MOSFET (TBCFET) is made for the first time and compared with single-bridge-channel MOSFET (SBCFET) and MBCFET

A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain : Application to Sub-50nm DRAM Cell

We have successfully fabricated fully integrated advanced RCAT (Recess Channel Array Transistor) featuring partially insulating oxide layers in bulk Si substrate, named Partially-insulated-RCAT (Pi-RCAT) to suppress body effect of conventional RCAT and improve current drivability in DRAM cell. The Pi-RCAT demonstrated superior characteristics in body effect, subthreshold slope (SW) and higher current drivability with comparable Ion-Ioff characteristics in comparison with conventional RCAT. Furthermore, in the partially-insulated-STI (Pi-STI) of core and peripheral structure formed simultaneously, well isolation characteristic is improved remarkably due to increase of effective isolation path. In this paper, Pi-RCAT is proved to be effective for the scalability and drivability of RCAT, and Pi-STI is suitable for the improvement of chip shrinkage efficiency.

High performance Silicon-On-ONO (SOONO) Cell Array Transistors (SCATs) for 512Mb DRAM Cell Array Application

As DRAM cell pitch size scales, the DRAM cells have required characteristics of high performance transistors. In this paper, we proposed and successfully demonstrated high performance silicon-on-ONO (SOONO) cell array transistors (SCATs) for 512Mb DRAM cell array application. They have advantages of SOI substrate and 3-D hi-gate as well as process simplicity. From those advantages, they have low Ioff due to good SCE immunity with DIBL of 40 mV/V and SS of 84 mV/dec, low GIDL current, low junction leakage current, and low junction capacitance as well as no body bias dependence. Thus, the SCATs may be a promising solution satisfying the requirements of DRAM cells with scaling.