Yonglu Wang

A two-stage low-power amplifier with switch-capacitor common-mode feedback circuits

A low-power amplifier is designed to improve the performances of ADCs. The two-stage construction is adopted to provide bigger gain and wider swing at a power supply lower than 3.3V. Besides, the differential architecture is adopted to double the output swing while suppressing common noises. Special common-mode feedback circuits are designed to stable the common-mode outputs of the first and second stages but not to degenerate the output swing. A private switch is designed for the common-mode feedback circuits to eliminate the charge injection effect on the common-mode signals. The measurement results show that the ADC using the proposed amplifier has a SNR which is 4dB better than the ADC without the proposed amplifier.

A multi-phase clock design for super high-speed time interleaved analog-to-digital converter

In this paper, we present a multi-phase clock (MPC) which is used in a super high-speed time interleaved analog-to-digital converter (TI ADC). To meet the timing requirements of the whole ADC, timing design between channels must be performed carefully, meanwhile, because the signal-to-noise ratio(SNR) of the whole ADC is restrained to the time-skew and jitter performance of the multi-phase clock, lower these timing errors is very important for TI ADC. We use a shift register based multi-phase generator to implement the multiphase relationship between sub-clocks. Digital calibration of the time-skew of single channel clock and serial peripheral interface (SPI) are adopted to lower timing errors between them further more. As a demonstration, a 4-phase clock is implemented, the presented clock circuit is used in a 8bit 5Gsps TI ADC. The whole TI ADC is implemented using a 0.18μm SiGe BiCMOS process. As a result of test, the whole ADC has a SNR of about 45dB at the input frequency of 495MHZ.

A novel track and hold circuit with offset and gain calibration

A novel track and hold circuit in 0.18μm SiGe BiCMOS process is presented, whose offset and gain can be digitally calibrated, and which can be used in a time-interleaved ADC to improve its performances. The simulated results show that the proposed track and hold circuit can sample a signal at a rate of 1.25GHz, while consuming just 50mW. The offset calibration can get a range of 26.6mW with a step of 0.1mW, while the gain calibration gets a range of 33.28dB with a step of 0.13dB.

Dynamic latched comparator design for super-high speed analog-to-digital converter

As a building block of analog-to-digital converter (ADC), comparator plays an important role, especially the case latched comparator for super-high speed ADC. The speed and performance of latched comparator mostly decide the performance of the whole ADC. In this paper, a multi-stage purely dynamic high speed latched comparator for folding and interpolating ADC is designed with Bi-CMOS 0.18um process technology. The folding and interpolating ADC is employed in a four channel time interleaved ADC as a sub-ADC. The whole ADC can reach a sampling rate of 5GSPS at interleaved mode. As a result of measurement, the whole ADC can get a SNR of 45dB with the input frequency of 495MHz at the sample rate of 5GHz.